From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC5113E95AE; Thu, 19 Mar 2026 16:11:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773936682; cv=none; b=GuTzIku/kcTOrV+STZVJc4zCEcs1ezQ+fmydQZ7gQDm+Vyo4/PvFm8onjk7RCXPxWs9Y43YuP0NIrB3DJK93ZzQmWnbO7hRXBB6OGk/oLBzSjvVqVVdfMExuuqn5goKwTRObUqH0lIIEFJiUbO/IflKaImLHqngM7wzwjURSo74= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773936682; c=relaxed/simple; bh=vg1UumV6k5QeDyVUBGRbAYWZNFDa34Na9e5e2zZwlhs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=pdsfeEDg8kOgWL7s7xH6r0EXzgnks71cOlxRvrCtjanUVIJftyYiEhXIhmRe2t69HvctyKQZyhP5PW5qFmO+RPB5O4s6Dl7i9YqM4gaC7Opv2yktMMttFEuPagLvuNWjRxfpRRCuAWxjB1wflWHxFjYsWB7ABUdGde1BNPmERdk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cj2rhpuX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cj2rhpuX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8B93DC2BCB0; Thu, 19 Mar 2026 16:11:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773936682; bh=vg1UumV6k5QeDyVUBGRbAYWZNFDa34Na9e5e2zZwlhs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=cj2rhpuXMDoK5LXQVXKFq+o4Gllw2HT76plU/UiNB4EYqlhsjDtc6IXH2xWq01zk2 uCW/5flYeuFOoyNPV6hWib0l3AmxLQ+FMwvyADuLwudzkc/CYxbaGBIk1jIEmpw7zx uJa0Vm2FUIGi1MKFjNYm05t2Nc/6vYvTzcWK6Gr1rMyXAvsTOuGWBTaLWCcor3P7FQ acw3om1B/4lqwcZnkpWwpjblcMnjaxWxlTs0sm+jk+Rl8s8t9GbP1iVyZbTbKndHEr gDCtck8FLN0wfYCKs6ueFGr9fkxZDuIRc0UNwaDSxdzcvJZ22jGnO6AdKhO6zvTj0q /FpidMuARFboQ== Message-ID: <353939e0-ef52-4c8f-bf71-ff27fa2c7d7a@kernel.org> Date: Thu, 19 Mar 2026 17:11:17 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller To: Thierry Reding , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jon Hunter , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org References: <20260319160110.2131954-1-thierry.reding@kernel.org> <20260319160110.2131954-4-thierry.reding@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 19/03/2026 17:01, Thierry Reding wrote: > From: Thierry Reding > > The six PCIe controllers found on Tegra264 are of two types: one is used > for the internal GPU and therefore is not connected to a UPHY and the > remaining five controllers are typically routed to a PCI slot and have > additional controls for the physical link. > > While these controllers can be switched into endpoint mode, this binding > describes the root complex mode only. > > Signed-off-by: Thierry Reding > --- > .../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml > new file mode 100644 > index 000000000000..56d69de2788b > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml > @@ -0,0 +1,92 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra264 PCIe controller > + > +maintainers: > + - Thierry Reding > + - Jon Hunter > + > +properties: > + compatible: > + const: nvidia,tegra264-pcie > + > + reg: > + minItems: 4 > + maxItems: 5 > + > + reg-names: > + minItems: 4 > + maxItems: 5 > + > + interrupts: > + minItems: 1 > + maxItems: 4 > + > + dma-coherent: true > + > + nvidia,bpmp: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + Must contain a pair of phandle (to the BPMP controller node) and > + controller ID. The following are the controller IDs for each controller: > + > + 0: C0 > + 1: C1 > + 2: C2 > + 3: C3 > + 4: C4 > + 5: C5 > + items: > + - items: > + - description: phandle to the BPMP controller node > + - description: PCIe controller ID > + maximum: 5 > + > +unevaluatedProperties: false This goes before example > + > +required: > + - interrupt-map > + - interrupt-map-mask > + - iommu-map > + - msi-map > + - nvidia,bpmp > + > +allOf: > + - $ref: /schemas/pci/pci-host-bridge.yaml# > + - oneOf: > + - description: C0 controller (no UPHY) It does not look like you tested the bindings, at least after quick look. Please run `make dt_binding_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions). Maybe you need to update your dtschema and yamllint. Don't rely on distro packages for dtschema and be sure you are using the latest released dtschema. > + properties: > + reg: > + items: > + - description: application layer registers > + - description: transaction layer registers > + - description: privileged transaction layer registers > + - description: ECAM-compatible configuration space > + > + reg-names: > + items: > + - const: xal > + - const: xtl > + - const: xtl-pri > + - const: ecam > + > + - description: C1-C5 controllers (with UPHY) > + properties: > + reg: > + items: > + - description: application layer registers > + - description: transaction layer registers > + - description: privileged transaction layer registers > + - description: data link/physical layer registers > + - description: ECAM-compatible configuration space > + > + items: > + - const: xal > + - const: xtl > + - const: xtl-pri > + - const: xpl > + - const: ecam All of above are part of top level. And speaking about example - where is it? How can you then test (verify) this? Best regards, Krzysztof