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Tue, 30 Jul 2024 22:44:20 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46UMiJFX019644 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 30 Jul 2024 22:44:19 GMT Received: from [10.110.63.167] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 30 Jul 2024 15:44:18 -0700 Message-ID: <35402164-dce0-b972-bf98-c025fe5620f0@quicinc.com> Date: Tue, 30 Jul 2024 15:44:06 -0700 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 4/5] thermal: qcom-spmi-temp-alarm: add support for GEN2 rev 2 PMIC peripherals Content-Language: en-US To: Dmitry Baryshkov CC: , , , , , , , , , , , , , , References: <20240729231259.2122976-1-quic_amelende@quicinc.com> <20240729231259.2122976-5-quic_amelende@quicinc.com> From: Anjelique Melendez In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fYnkxKTnxcwsEnfeiuEGqL0KpYdOSqRH X-Proofpoint-GUID: fYnkxKTnxcwsEnfeiuEGqL0KpYdOSqRH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-30_18,2024-07-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1011 bulkscore=0 adultscore=0 suspectscore=0 malwarescore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407300157 >> >> +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ >> +static int qpnp_tm_gen2_rev2_update_trip_temps(struct qpnp_tm_chip *chip) >> +{ >> + struct thermal_trip trip = {0}; >> + int ret, ntrips, i; >> + >> + ntrips = thermal_zone_get_num_trips(chip->tz_dev); >> + /* Keep hardware defaults if no DT trips are defined. */ >> + if (ntrips <= 0) >> + return 0; >> + >> + for (i = 0; i < ntrips; i++) { >> + ret = thermal_zone_get_trip(chip->tz_dev, i, &trip); >> + if (ret < 0) >> + return ret; >> + >> + ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, i, trip.temperature); >> + if (ret < 0) >> + return ret; >> + } >> + >> + /* Verify that trips are strictly increasing. */ > > There is no such requirement in the DT bindings. Please don't invent > artificial restrictions, especially if they are undocumented. > This is not an entirely new restirction. Currently the temp alarm driver has hardcoded temperature thresholds options which are "strictly increasing" (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/thermal/qcom/qcom-spmi-temp-alarm.c?h=v6.11-rc1#n44). The threshold values are initially configured based on the stage 2 critical trip temperature. For newer PMICs, we have individual temperature registers for stage 1, 2, and 3, so we instead configure each threshold temperature as defined in DT. In general since stage 1 = warning, stage 2 = system should shut down, stage 3 = emergency shutdown, we would expect for temperature thresholds to increase for each stage (https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/thermal?h=v5.4.281&id=f1599f9e4cd6f1dd0cad202853fb830854f4e944). I agree that we are missing some documentation but since the trips are defined in the thermal_zone node what is the best way to mention this requirement? Will adding a few sentences to qcom,spmi-temp-alarm.yaml description be enough? Do we need to make changes to thermal_zone.yaml so that dt_binding_check catches this requirement? >> + for (i = 1; i < STAGE_COUNT; i++) { >> + if (chip->temp_dac_map[i] <= chip->temp_dac_map[i - 1]) { >> + dev_err(chip->dev, "Threshold %d=%ld <= threshold %d=%ld\n", >> + i, chip->temp_dac_map[i], i - 1, >> + chip->temp_dac_map[i - 1]); >> + return -EINVAL; >> + } >> + } >> + >> + return 0; Thanks, Anjelique