Re: [PATCH v6] SATA: OCTEON: support SATA on OCTEON platform

[Arnd Bergmann <arnd@arndb.de>]

On Wednesday 03 February 2016 13:24:10 Zubair Lutfullah Kakakhel wrote:
> 
> Bitfields for both endians are used and handled by mips.
> Mainly used by cavium.
> 
> As this is a cavium driver, would it be acceptable?
> 
> Or should I replace with the following.
> 
>         v = cvmx_read_csr((uint64_t)base + CVMX_SATA_UCTL_SHIM_CFG);
>         v &= ~(SATA_UCTL_ENDIAN_MODE_E_MASK << DMA_ENDIAN_MODE);
>         v &= ~(SATA_UCTL_ENDIAN_MODE_E_MASK << CSR_ENDIAN_MODE);
> #ifdef __BIG_ENDIAN
>         v |= SATA_UCTL_ENDIAN_MODE_E_BIG << DMA_ENDIAN_MODE;
>         v |= SATA_UCTL_ENDIAN_MODE_E_BIG << CSR_ENDIAN_MODE;
> #else
>         v |= SATA_UCTL_ENDIAN_MODE_E_LITTLE << DMA_ENDIAN_MODE;
>         v |= SATA_UCTL_ENDIAN_MODE_E_LITTLE << CSR_ENDIAN_MODE;
> #endif
>         v |= 1 << DMA_READ_CMD;
>         cvmx_write_csr((uint64_t)base + CVMX_SATA_UCTL_SHIM_CFG, v);

I think something like this would be more conventional, yes. Or maybe
define the macros so you don't have to do the shift everywhere:

         v &= ~SATA_UCTL_ENDIAN_MODE_E_MASK | SATA_UCTL_ENDIAN_MODE | SATA_UCTL_DMA_READ_CMD;

	Arnd