Re: [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree

["Heiko Stübner" <heiko@sntech.de>]

Am Montag, 8. Mai 2023, 10:35:38 CEST schrieb Conor Dooley:
> On Mon, May 08, 2023 at 10:23:02AM +0200, Heiko Stübner wrote:
> > Am Montag, 8. Mai 2023, 05:32:17 CEST schrieb Icenowy Zheng:
> > > 在 2023-05-07星期日的 22:35 +0100，Conor Dooley写道：
> > > > Hey Jisheng,
> > > > 
> > > > On Mon, May 08, 2023 at 02:23:02AM +0800, Jisheng Zhang wrote:
> > > > 
> > > > > +               c910_0: cpu@0 {
> > > > > +                       compatible = "thead,c910", "riscv";
> > > > > +                       device_type = "cpu";
> > > > > +                       riscv,isa = "rv64imafdc";
> > > > 
> > > > Does this support more than "rv64imafdc"?
> > > > I assume there's some _xtheadfoo extensions that it does support,
> > > > although I am not sure how we are proceeding with those - Heiko might
> > > > have a more nuanced take.
> > 
> > I guess the interesting question still is, are these part of the isa
> > string or more of an errata?
> 
> Yeah, I dunno. That's possible a policy decision more than anything
> else. I don't remember if it was one of your patchsets or elsewhere, but
> I do recall a split between xtheadba etc and vector, where xtheadba was
> defined as a vendor extension, whereas vector is not. Their extension
> spec repo <https://github.com/T-head-Semi/thead-extension-spec> appears
> to be aligned with that view, apart from the CMOs that we have already
> called an erratum.

I think the CMO stuff came a bit before that repo actually existed ;-) .

I guess another argument for riscv,isa would be that we don't have to
trust MVENDORID, and especially values in MARCHID and MIMPID.

Somehow part of me doesn't have enough trust that these values will
always be suitably different when they are baked into the hardware ;-) .


I guess vector is somewhat special, with it implementing version 0.7.1
it's not a t-head invention but also not the real RISCV "v" .

So I _guess_ the jury might still be out on how to handle that everywhere.


> > The binding currently says
> >       Identifies the specific RISC-V instruction set architecture
> >       supported by the hart.  These are documented in the RISC-V
> >       User-Level ISA document, available from
> >       https://riscv.org/specifications/
> > 
> > 
> > I guess if we decide to make them part of the isa-string the binding
> > then should get a paragraph mention _xfoo vendor-extensions too.
> 
> I have an idea in the works that may allow dealing with this kind of
> thing, but it's a bit of a departure from the existing binding.
> I will hopefully post an early RFC of it later today.
> That said, the binding does currently allow you to put in _xfoo vendor
> extensions as-is.
> 
> > Personally, making these part of the ISA string definitly sounds like
> > the best solution though :-) .
> 
> You would say that wouldn't you! In general, I'd rather we filled in as
> much information as possible here, even if it is not currently in use,
> to avoid having to retrofit as support becomes available.

yep definitively.
Especially as switching to expecting _xfoo later on then causes of course
compatiblity issues. The fun part will be though to get vendors,
toolchains and friends to agree on the naming.


Heiko