Re: [PATCH v5 2/2] thermal: Add support for Airoha EN7581 thermal sensor

[Daniel Lezcano <daniel.lezcano@linaro.org>]

Hi Angelo,

AFAIR, the LVTS driver had issues with the interrupts.

This driver proposed by Ansuel Smith looks very similar to the LVTS and 
there are some comments regarding errors with the documentation below 
which may appy to the LVTS driver too.

Would you mind to check ?

See below.

On 26/02/2025 01:35, Christian Marangi wrote:
> Add support for Airoha EN7581 thermal sensor. This provide support for
> reading the CPU or SoC Package sensor and to setup trip points for hot
> and critical condition. An interrupt is fired to react on this and
> doesn't require passive poll to read the temperature.
> 
> The thermal regs provide a way to read the ADC value from an external
> register placed in the Chip SCU regs. Monitor will read this value and
> fire an interrupt if the trip condition configured is reached.
> 
> The Thermal Trip and Interrupt logic is conceptually similar to Mediatek
> LVTS Thermal but differ in register mapping and actual function/bug
> workaround. The implementation only share some register names but from
> functionality observation it's very different and used only for the
> basic function of periodically poll the temp and trip the interrupt.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---

[ ... ]

> +#define   EN7581_HINTEN1			BIT(6)
> +#define   EN7581_CINTEN1			BIT(5)
> +#define   EN7581_NOHOTINTEN0			BIT(4)
> +/* Similar to COLD and HOT also these seems to be swapped in documentation */
> +#define   EN7581_LOFSINTEN0			BIT(3) /* In documentation: BIT(2) */
> +#define   EN7581_HOFSINTEN0			BIT(2) /* In documentation: BIT(3) */
> +/* It seems documentation have these swapped as the HW
> + * - Fire BIT(1) when lower than EN7581_COLD_THRE
> + * - Fire BIT(0) and BIT(5) when higher than EN7581_HOT2NORMAL_THRE or
> + *     EN7581_HOT_THRE
> + */
> +#define   EN7581_CINTEN0			BIT(1) /* In documentation: BIT(0) */
> +#define   EN7581_HINTEN0			BIT(0) /* In documentation: BIT(1) */
> +#define EN7581_TEMPMONINTSTS			0x810
> +#define   EN7581_STAGE3_INT_STAT		BIT(31)
> +#define   EN7581_STAGE2_INT_STAT		BIT(30)
> +#define   EN7581_STAGE1_INT_STAT		BIT(29)
> +#define   EN7581_FILTER_INT_STAT_3		BIT(28)

[ ... ]

> +#define   EN7581_NOHOTINTSTS0			BIT(4)
> +/* Similar to COLD and HOT also these seems to be swapped in documentation */
> +#define   EN7581_LOFSINTSTS0			BIT(3) /* In documentation: BIT(2) */
> +#define   EN7581_HOFSINTSTS0			BIT(2) /* In documentation: BIT(3) */
> +/* It seems documentation have these swapped as the HW
> + * - Fire BIT(1) when lower than EN7581_COLD_THRE
> + * - Fire BIT(0) and BIT(5) when higher than EN7581_HOT2NORMAL_THRE or
> + *     EN7581_HOT_THRE
> + *
> + * To clear things, we swap the define but we keep them documented here.
> + */
> +#define   EN7581_CINTSTS0			BIT(1) /* In documentation: BIT(0) */
> +#define   EN7581_HINTSTS0			BIT(0) /* In documentation: BIT(1)*/
> +/* Monitor will take the bigger threshold between HOT2NORMAL and HOT
> + * and will fire both HOT2NORMAL and HOT interrupt when higher than the 2
> + *
> + * It has also been observed that not setting HOT2NORMAL makes the monitor
> + * treat COLD threshold as HOT2NORMAL.
> + */
> +#define EN7581_TEMPH2NTHRE			0x824
> +/* It seems HOT2NORMAL is actually NORMAL2HOT */
> +#define   EN7581_HOT2NORMAL_THRE		GENMASK(11, 0)
> +#define EN7581_TEMPHTHRE			0x828
> +#define   EN7581_HOT_THRE			GENMASK(11, 0)
> +/* Monitor will use this as HOT2NORMAL (fire interrupt when lower than...)*/
> +#define EN7581_TEMPCTHRE			0x82c
> +#define   EN7581_COLD_THRE			GENMASK(11, 0)
> +/* Also LOW and HIGH offset register are swapped */
> +#define EN7581_TEMPOFFSETL			0x830 /* In documentation: 0x834 */
> +#define   EN7581_LOW_OFFSET			GENMASK(11, 0)
> +#define EN7581_TEMPOFFSETH			0x834 /* In documentation: 0x830 */
> +#define   EN7581_HIGH_OFFSET			GENMASK(11, 0)
> +#define EN7581_TEMPMSRCTL0			0x838

[ ... ]





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