From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA7E7C43461 for ; Tue, 15 Sep 2020 18:42:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 938CA20B1F for ; Tue, 15 Sep 2020 18:42:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Mh/8xoiP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727411AbgIOSmm (ORCPT ); Tue, 15 Sep 2020 14:42:42 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:60624 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727685AbgIOSmZ (ORCPT ); Tue, 15 Sep 2020 14:42:25 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08FFSnJ0003042; Tue, 15 Sep 2020 10:28:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600183729; bh=HKPqFeP1xgYZAUPIJMNKl6DC2xxeRZjq9DPsJ7FtVqg=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=Mh/8xoiP/YMcouQhi8Lcvd2H0PyAq7ph3yLDYttLG74Ib66/YBvt0AwgAkyhAb2aF Qc++bUiIMyIB9+C4nNxCAOMNh4twHBvXXJc5ABw0pNuxTxrtGY8DszJlZuRHVGvq9T kTKtVaUc1m1WaPd353T5JKp4c0dGxVLM+LZFecbI= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08FFSmUY002448 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 15 Sep 2020 10:28:48 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 15 Sep 2020 10:28:48 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 15 Sep 2020 10:28:48 -0500 Received: from [10.250.66.210] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08FFSlvF071083; Tue, 15 Sep 2020 10:28:48 -0500 Subject: Re: [PATCH v4 3/5] dt-bindings: arm: ti: Add bindings for J7200 SoC To: Lokesh Vutla , Nishanth Menon , Tero Kristo , Rob Herring CC: Linux ARM Mailing List , Device Tree Mailing List , Sekhar Nori , Grygorii Strashko , Kishon Vijay Abraham I References: <20200914162231.2535-1-lokeshvutla@ti.com> <20200914162231.2535-4-lokeshvutla@ti.com> From: Suman Anna Message-ID: <3599ad10-71b5-cb27-0af0-fee2c079ff9b@ti.com> Date: Tue, 15 Sep 2020 10:28:47 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200914162231.2535-4-lokeshvutla@ti.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 9/14/20 11:22 AM, Lokesh Vutla wrote: > The J7200 SoC is a part of the K3 Multicore SoC architecture platform. > It is targeted for automotive gateway, vehicle compute systems, > Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. > The SoC aims to meet the complex processing needs of modern embedded > products. > > Some highlights of this SoC are: > * Dual Cortex-A72s in a single cluster, two clusters of lockstep > capable dual Cortex-R5F MCUs and a Centralized Device Management and > Security Controller (DMSC). > * Configurable L3 Cache and IO-coherent architecture with high data > throughput capable distributed DMA architecture under NAVSS. > * Integrated Ethernet switch supporting up to a total of 4 external ports > in addition to legacy Ethernet switch of up to 2 ports. > * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, > 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and > I2C, eCAP/eQEP, eHRPWM among other peripherals. > * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL > management. > > See J7200 Technical Reference Manual (SPRUIU1, June 2020) > for further details: https://www.ti.com/lit/pdf/spruiu1 > > Reviewed-by: Grygorii Strashko > Signed-off-by: Lokesh Vutla Reviewed-by: Suman Anna regards Suman > --- > Documentation/devicetree/bindings/arm/ti/k3.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml > index c5e3e4aeda8e..829751209543 100644 > --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml > +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml > @@ -28,4 +28,8 @@ properties: > - description: K3 J721E SoC > items: > - const: ti,j721e > + > + - description: K3 J7200 SoC > + items: > + - const: ti,j7200 > ... >