[PATCH v4 0/5] arm64: qcom: sm8x50: enable RNG

[PATCH v4 0/5] arm64: qcom: sm8x50: enable RNG

[Neil Armstrong]

Enable RNG on SM8550 & SM8450 by reverting the PRNG bindings & DT
for SM8450 and correctly document it as a True Random Number Generator.

- SM8550 QRD test run:

smccc_trng qcom_hwrng 

qcom_hwrng

rngtest 6.15
Copyright (c) 2004 by Henrique de Moraes Holschuh
This is free software; see the source for copying conditions.  There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

rngtest: starting FIPS tests...
rngtest: bits received from input: 209420032
rngtest: FIPS 140-2 successes: 10461
rngtest: FIPS 140-2 failures: 10
rngtest: FIPS 140-2(2001-10-10) Monobit: 1
rngtest: FIPS 140-2(2001-10-10) Poker: 2
rngtest: FIPS 140-2(2001-10-10) Runs: 3
rngtest: FIPS 140-2(2001-10-10) Long run: 4
rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
rngtest: input channel speed: (min=9.219; avg=63.879; max=19073.486)Mibits/s
rngtest: FIPS tests speed: (min=24.965; avg=29.093; max=118.469)Mibits/s
rngtest: Program run time: 10002827 microseconds

- SM8450 HDK test run:

qcom_hwrng

rngtest 6.15
Copyright (c) 2004 by Henrique de Moraes Holschuh
This is free software; see the source for copying conditions.  There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

rngtest: starting FIPS tests...
rngtest: bits received from input: 420580032
rngtest: FIPS 140-2 successes: 21014
rngtest: FIPS 140-2 failures: 15
rngtest: FIPS 140-2(2001-10-10) Monobit: 2
rngtest: FIPS 140-2(2001-10-10) Poker: 0
rngtest: FIPS 140-2(2001-10-10) Runs: 7
rngtest: FIPS 140-2(2001-10-10) Long run: 6
rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
rngtest: input channel speed: (min=15.711; avg=50.033; max=32.493)Mibits/s
rngtest: FIPS tests speed: (min=136.239; avg=203.833; max=227.065)Mibits/s
rngtest: Program run time: 10000978 microseconds

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v4:
- changed to an enum in first bindings patch to simplify sm8550 change
- integrate Om's patch from (https://lore.kernel.org/all/20230926102005.3277045-1-quic_omprsing@quicinc.com)
  to simplify maintainer's life
- rebased on next-20230929
- dropped already applied revert
- Link to v3: https://lore.kernel.org/r/20230828-topic-sm8550-rng-v3-0-7a0678ca7988@linaro.org

Changes in v3:
- Removed invalid character in commit msg
- Added review tags
- Removed applied patch 1
- Link to v2: https://lore.kernel.org/r/20230824-topic-sm8550-rng-v2-0-dfcafbb16a3e@linaro.org

Changes in v2:
- Revert SM8450 DT & bindings
- Add new qcom,trng compatible and use it for SM8450 & SM8550
- Explicitly didn't collect the Reviewed-by tags due to the compatible change
- Link to v1: https://lore.kernel.org/r/20230822-topic-sm8550-rng-v1-0-8e10055165d1@linaro.org

---
Neil Armstrong (4):
      dt-bindings: crypto: qcom,prng: document that RNG on SM8450 is a TRNG
      dt-bindings: crypto: qcom,prng: document SM8550
      arm64: dts: qcom: sm8550: add TRNG node
      arm64: dts: qcom: sm8450: add TRNG node

Om Prakash Singh (1):
      crypto: qcom-rng - Add hw_random interface support

 .../devicetree/bindings/crypto/qcom,prng.yaml      | 26 +++++++--
 arch/arm64/boot/dts/qcom/sm8450.dtsi               |  5 ++
 arch/arm64/boot/dts/qcom/sm8550.dtsi               |  5 ++
 drivers/crypto/qcom-rng.c                          | 65 +++++++++++++++++++---
 4 files changed, 89 insertions(+), 12 deletions(-)
---
base-commit: df964ce9ef9fea10cf131bf6bad8658fde7956f6
change-id: 20230822-topic-sm8550-rng-c83142783e20

Best regards,
-- 
Neil Armstrong <neil.armstrong@linaro.org>

[PATCH v4 1/5] dt-bindings: crypto: qcom,prng: document that RNG on SM8450 is a TRNG

[Neil Armstrong]

It has been reported at [1] the RNG HW on SM8450 is in fact a True Random
Number Generator and no more Pseudo, document this by adding
a new qcom,trng and the corresponding SoC specific sm8450 compatible.

[1] https://lore.kernel.org/all/20230818161720.3644424-1-quic_omprsing@quicinc.com/

Suggested-by: Om Prakash Singh <quic_omprsing@quicinc.com>
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Om Prakash Singh <quic_omprsing@quicinc.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 .../devicetree/bindings/crypto/qcom,prng.yaml      | 25 +++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
index bb42f4588b40..04ddcc0f7165 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
@@ -11,9 +11,14 @@ maintainers:
 
 properties:
   compatible:
-    enum:
-      - qcom,prng  # 8916 etc.
-      - qcom,prng-ee  # 8996 and later using EE
+    oneOf:
+      - enum:
+          - qcom,prng  # 8916 etc.
+          - qcom,prng-ee  # 8996 and later using EE
+      - items:
+          - enum:
+              - qcom,sm8450-trng
+          - const: qcom,trng
 
   reg:
     maxItems: 1
@@ -28,8 +33,18 @@ properties:
 required:
   - compatible
   - reg
-  - clocks
-  - clock-names
+
+allOf:
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              const: qcom,trng
+    then:
+      required:
+        - clocks
+        - clock-names
 
 additionalProperties: false
 

-- 
2.34.1

[PATCH v4 2/5] dt-bindings: crypto: qcom,prng: document SM8550

[Neil Armstrong]

Document SM8550 compatible for the True Random Number Generator.

Reviewed-by: Om Prakash Singh <quic_omprsing@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
index 04ddcc0f7165..633993f801c6 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
@@ -18,6 +18,7 @@ properties:
       - items:
           - enum:
               - qcom,sm8450-trng
+              - qcom,sm8550-trng
           - const: qcom,trng
 
   reg:

-- 
2.34.1

[PATCH v4 3/5] crypto: qcom-rng - Add hw_random interface support

[neil.armstrong]

From: Om Prakash Singh <quic_omprsing@quicinc.com>

Add hw_random interface support in qcom-rng driver as new IP block
in Qualcomm SoC has inbuilt NIST SP800 90B compliant entropic source
to generate true random number.

Keeping current rng_alg interface as well for random number generation
using Kernel Crypto API.

Signed-off-by: Om Prakash Singh <quic_omprsing@quicinc.com>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/crypto/qcom-rng.c | 65 ++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 58 insertions(+), 7 deletions(-)

diff --git a/drivers/crypto/qcom-rng.c b/drivers/crypto/qcom-rng.c
index 825a729f205e..8b506abb934c 100644
--- a/drivers/crypto/qcom-rng.c
+++ b/drivers/crypto/qcom-rng.c
@@ -7,6 +7,7 @@
 #include <linux/acpi.h>
 #include <linux/clk.h>
 #include <linux/crypto.h>
+#include <linux/hw_random.h>
 #include <linux/io.h>
 #include <linux/iopoll.h>
 #include <linux/kernel.h>
@@ -28,17 +29,25 @@
 
 #define WORD_SZ			4
 
+#define QCOM_TRNG_QUALITY	1024
+
 struct qcom_rng {
 	struct mutex lock;
 	void __iomem *base;
 	struct clk *clk;
-	unsigned int skip_init;
+	struct hwrng hwrng;
+	struct qcom_rng_of_data *of_data;
 };
 
 struct qcom_rng_ctx {
 	struct qcom_rng *rng;
 };
 
+struct qcom_rng_of_data {
+	bool skip_init;
+	bool hwrng_support;
+};
+
 static struct qcom_rng *qcom_rng_dev;
 
 static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
@@ -66,11 +75,11 @@ static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
 		} else {
 			/* copy only remaining bytes */
 			memcpy(data, &val, max - currsize);
-			break;
+			currsize = max;
 		}
 	} while (currsize < max);
 
-	return 0;
+	return currsize;
 }
 
 static int qcom_rng_generate(struct crypto_rng *tfm,
@@ -92,6 +101,9 @@ static int qcom_rng_generate(struct crypto_rng *tfm,
 	mutex_unlock(&rng->lock);
 	clk_disable_unprepare(rng->clk);
 
+	if (ret >= 0)
+		ret = 0;
+
 	return ret;
 }
 
@@ -101,6 +113,13 @@ static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed,
 	return 0;
 }
 
+static int qcom_hwrng_read(struct hwrng *hwrng, void *data, size_t max, bool wait)
+{
+	struct qcom_rng *qrng = container_of(hwrng, struct qcom_rng, hwrng);
+
+	return qcom_rng_read(qrng, data, max);
+}
+
 static int qcom_rng_enable(struct qcom_rng *rng)
 {
 	u32 val;
@@ -136,7 +155,7 @@ static int qcom_rng_init(struct crypto_tfm *tfm)
 
 	ctx->rng = qcom_rng_dev;
 
-	if (!ctx->rng->skip_init)
+	if (!ctx->rng->of_data->skip_init)
 		return qcom_rng_enable(ctx->rng);
 
 	return 0;
@@ -177,15 +196,31 @@ static int qcom_rng_probe(struct platform_device *pdev)
 	if (IS_ERR(rng->clk))
 		return PTR_ERR(rng->clk);
 
-	rng->skip_init = (unsigned long)device_get_match_data(&pdev->dev);
+	rng->of_data = (struct qcom_rng_of_data *)of_device_get_match_data(&pdev->dev);
 
 	qcom_rng_dev = rng;
 	ret = crypto_register_rng(&qcom_rng_alg);
 	if (ret) {
 		dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
 		qcom_rng_dev = NULL;
+		return ret;
+	}
+
+	if (rng->of_data->hwrng_support) {
+		rng->hwrng.name = "qcom_hwrng";
+		rng->hwrng.read = qcom_hwrng_read;
+		rng->hwrng.quality = QCOM_TRNG_QUALITY;
+		ret = devm_hwrng_register(&pdev->dev, &rng->hwrng);
+		if (ret) {
+			dev_err(&pdev->dev, "Register hwrng failed: %d\n", ret);
+			qcom_rng_dev = NULL;
+			goto fail;
+		}
 	}
 
+	return ret;
+fail:
+	crypto_unregister_rng(&qcom_rng_alg);
 	return ret;
 }
 
@@ -198,6 +233,21 @@ static int qcom_rng_remove(struct platform_device *pdev)
 	return 0;
 }
 
+struct qcom_rng_of_data qcom_prng_of_data = {
+	.skip_init = false,
+	.hwrng_support = false,
+};
+
+struct qcom_rng_of_data qcom_prng_ee_of_data = {
+	.skip_init = true,
+	.hwrng_support = false,
+};
+
+struct qcom_rng_of_data qcom_trng_of_data = {
+	.skip_init = true,
+	.hwrng_support = true,
+};
+
 static const struct acpi_device_id __maybe_unused qcom_rng_acpi_match[] = {
 	{ .id = "QCOM8160", .driver_data = 1 },
 	{}
@@ -205,8 +255,9 @@ static const struct acpi_device_id __maybe_unused qcom_rng_acpi_match[] = {
 MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match);
 
 static const struct of_device_id __maybe_unused qcom_rng_of_match[] = {
-	{ .compatible = "qcom,prng", .data = (void *)0},
-	{ .compatible = "qcom,prng-ee", .data = (void *)1},
+	{ .compatible = "qcom,prng", .data = &qcom_prng_of_data },
+	{ .compatible = "qcom,prng-ee", .data = &qcom_prng_ee_of_data },
+	{ .compatible = "qcom,trng", .data = &qcom_trng_of_data },
 	{}
 };
 MODULE_DEVICE_TABLE(of, qcom_rng_of_match);

-- 
2.34.1

[PATCH v4 4/5] arm64: dts: qcom: sm8550: add TRNG node

[Neil Armstrong]

Add the Qualcomm True Random Number Generator node.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 7b9ddde0b2c9..7bafb3d88d69 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1677,6 +1677,11 @@ mmss_noc: interconnect@1780000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		rng: rng@10c3000 {
+			compatible = "qcom,sm8550-trng", "qcom,trng";
+			reg = <0 0x010c3000 0 0x1000>;
+		};
+
 		pcie0: pci@1c00000 {
 			device_type = "pci";
 			compatible = "qcom,pcie-sm8550";

-- 
2.34.1

[PATCH v4 5/5] arm64: dts: qcom: sm8450: add TRNG node

[Neil Armstrong]

The SM8450 SoC has a True Random Number Generator, add the node with
the correct compatible set.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 1783fa78bdbc..bde9c1093384 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1739,6 +1739,11 @@ spi14: spi@a98000 {
 			};
 		};
 
+		rng: rng@10c3000 {
+			compatible = "qcom,sm8450-trng", "qcom,trng";
+			reg = <0 0x010c3000 0 0x1000>;
+		};
+
 		pcie0: pci@1c00000 {
 			compatible = "qcom,pcie-sm8450-pcie0";
 			reg = <0 0x01c00000 0 0x3000>,

-- 
2.34.1

Re: [PATCH v4 1/5] dt-bindings: crypto: qcom,prng: document that RNG on SM8450 is a TRNG

[Krzysztof Kozlowski]

On 03/10/2023 09:10, Neil Armstrong wrote:
> It has been reported at [1] the RNG HW on SM8450 is in fact a True Random
> Number Generator and no more Pseudo, document this by adding
> a new qcom,trng and the corresponding SoC specific sm8450 compatible.
> 
> [1] https://lore.kernel.org/all/20230818161720.3644424-1-quic_omprsing@quicinc.com/
> 
> Suggested-by: Om Prakash Singh <quic_omprsing@quicinc.com>
> Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Reviewed-by: Om Prakash Singh <quic_omprsing@quicinc.com>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v4 0/5] arm64: qcom: sm8x50: enable RNG

[Vinod Koul]

On 03-10-23, 09:10, Neil Armstrong wrote:
> Enable RNG on SM8550 & SM8450 by reverting the PRNG bindings & DT
> for SM8450 and correctly document it as a True Random Number Generator.
> 
> - SM8550 QRD test run:
> 
> smccc_trng qcom_hwrng 
> 
> qcom_hwrng
> 
> rngtest 6.15
> Copyright (c) 2004 by Henrique de Moraes Holschuh
> This is free software; see the source for copying conditions.  There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
> 
> rngtest: starting FIPS tests...
> rngtest: bits received from input: 209420032
> rngtest: FIPS 140-2 successes: 10461
> rngtest: FIPS 140-2 failures: 10
> rngtest: FIPS 140-2(2001-10-10) Monobit: 1
> rngtest: FIPS 140-2(2001-10-10) Poker: 2
> rngtest: FIPS 140-2(2001-10-10) Runs: 3
> rngtest: FIPS 140-2(2001-10-10) Long run: 4
> rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
> rngtest: input channel speed: (min=9.219; avg=63.879; max=19073.486)Mibits/s
> rngtest: FIPS tests speed: (min=24.965; avg=29.093; max=118.469)Mibits/s
> rngtest: Program run time: 10002827 microseconds
> 
> - SM8450 HDK test run:
> 
> qcom_hwrng
> 
> rngtest 6.15
> Copyright (c) 2004 by Henrique de Moraes Holschuh
> This is free software; see the source for copying conditions.  There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
> 
> rngtest: starting FIPS tests...
> rngtest: bits received from input: 420580032
> rngtest: FIPS 140-2 successes: 21014
> rngtest: FIPS 140-2 failures: 15
> rngtest: FIPS 140-2(2001-10-10) Monobit: 2
> rngtest: FIPS 140-2(2001-10-10) Poker: 0
> rngtest: FIPS 140-2(2001-10-10) Runs: 7
> rngtest: FIPS 140-2(2001-10-10) Long run: 6
> rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
> rngtest: input channel speed: (min=15.711; avg=50.033; max=32.493)Mibits/s
> rngtest: FIPS tests speed: (min=136.239; avg=203.833; max=227.065)Mibits/s
> rngtest: Program run time: 10000978 microseconds

Acked-by: Vinod Koul <vkoul@kernel.org>

-- 
~Vinod

Re: [PATCH v4 3/5] crypto: qcom-rng - Add hw_random interface support

[Om Prakash Singh]

On 10/3/2023 12:40 PM, neil.armstrong@linaro.org wrote:
> From: Om Prakash Singh <quic_omprsing@quicinc.com>
> 
> Add hw_random interface support in qcom-rng driver as new IP block
> in Qualcomm SoC has inbuilt NIST SP800 90B compliant entropic source
> to generate true random number.
> 
> Keeping current rng_alg interface as well for random number generation
> using Kernel Crypto API.
> 
> Signed-off-by: Om Prakash Singh <quic_omprsing@quicinc.com>
> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---

Acked-by: Om Prakash Singh <quic_omprsing@quicinc.com>

>   drivers/crypto/qcom-rng.c | 65 ++++++++++++++++++++++++++++++++++++++++++-----
>   1 file changed, 58 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/crypto/qcom-rng.c b/drivers/crypto/qcom-rng.c
> index 825a729f205e..8b506abb934c 100644
> --- a/drivers/crypto/qcom-rng.c
> +++ b/drivers/crypto/qcom-rng.c
> @@ -7,6 +7,7 @@
>   #include <linux/acpi.h>
>   #include <linux/clk.h>
>   #include <linux/crypto.h>
> +#include <linux/hw_random.h>
>   #include <linux/io.h>
>   #include <linux/iopoll.h>
>   #include <linux/kernel.h>
> @@ -28,17 +29,25 @@
>   
>   #define WORD_SZ			4
>   
> +#define QCOM_TRNG_QUALITY	1024
> +
>   struct qcom_rng {
>   	struct mutex lock;
>   	void __iomem *base;
>   	struct clk *clk;
> -	unsigned int skip_init;
> +	struct hwrng hwrng;
> +	struct qcom_rng_of_data *of_data;
>   };
>   
>   struct qcom_rng_ctx {
>   	struct qcom_rng *rng;
>   };
>   
> +struct qcom_rng_of_data {
> +	bool skip_init;
> +	bool hwrng_support;
> +};
> +
>   static struct qcom_rng *qcom_rng_dev;
>   
>   static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
> @@ -66,11 +75,11 @@ static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
>   		} else {
>   			/* copy only remaining bytes */
>   			memcpy(data, &val, max - currsize);
> -			break;
> +			currsize = max;
>   		}
>   	} while (currsize < max);
>   
> -	return 0;
> +	return currsize;
>   }
>   
>   static int qcom_rng_generate(struct crypto_rng *tfm,
> @@ -92,6 +101,9 @@ static int qcom_rng_generate(struct crypto_rng *tfm,
>   	mutex_unlock(&rng->lock);
>   	clk_disable_unprepare(rng->clk);
>   
> +	if (ret >= 0)
> +		ret = 0;
> +
>   	return ret;
>   }
>   
> @@ -101,6 +113,13 @@ static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed,
>   	return 0;
>   }
>   
> +static int qcom_hwrng_read(struct hwrng *hwrng, void *data, size_t max, bool wait)
> +{
> +	struct qcom_rng *qrng = container_of(hwrng, struct qcom_rng, hwrng);
> +
> +	return qcom_rng_read(qrng, data, max);
> +}
> +
>   static int qcom_rng_enable(struct qcom_rng *rng)
>   {
>   	u32 val;
> @@ -136,7 +155,7 @@ static int qcom_rng_init(struct crypto_tfm *tfm)
>   
>   	ctx->rng = qcom_rng_dev;
>   
> -	if (!ctx->rng->skip_init)
> +	if (!ctx->rng->of_data->skip_init)
>   		return qcom_rng_enable(ctx->rng);
>   
>   	return 0;
> @@ -177,15 +196,31 @@ static int qcom_rng_probe(struct platform_device *pdev)
>   	if (IS_ERR(rng->clk))
>   		return PTR_ERR(rng->clk);
>   
> -	rng->skip_init = (unsigned long)device_get_match_data(&pdev->dev);
> +	rng->of_data = (struct qcom_rng_of_data *)of_device_get_match_data(&pdev->dev);
>   
>   	qcom_rng_dev = rng;
>   	ret = crypto_register_rng(&qcom_rng_alg);
>   	if (ret) {
>   		dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
>   		qcom_rng_dev = NULL;
> +		return ret;
> +	}
> +
> +	if (rng->of_data->hwrng_support) {
> +		rng->hwrng.name = "qcom_hwrng";
> +		rng->hwrng.read = qcom_hwrng_read;
> +		rng->hwrng.quality = QCOM_TRNG_QUALITY;
> +		ret = devm_hwrng_register(&pdev->dev, &rng->hwrng);
> +		if (ret) {
> +			dev_err(&pdev->dev, "Register hwrng failed: %d\n", ret);
> +			qcom_rng_dev = NULL;
> +			goto fail;
> +		}
>   	}
>   
> +	return ret;
> +fail:
> +	crypto_unregister_rng(&qcom_rng_alg);
>   	return ret;
>   }
>   
> @@ -198,6 +233,21 @@ static int qcom_rng_remove(struct platform_device *pdev)
>   	return 0;
>   }
>   
> +struct qcom_rng_of_data qcom_prng_of_data = {
> +	.skip_init = false,
> +	.hwrng_support = false,
> +};
> +
> +struct qcom_rng_of_data qcom_prng_ee_of_data = {
> +	.skip_init = true,
> +	.hwrng_support = false,
> +};
> +
> +struct qcom_rng_of_data qcom_trng_of_data = {
> +	.skip_init = true,
> +	.hwrng_support = true,
> +};
> +
>   static const struct acpi_device_id __maybe_unused qcom_rng_acpi_match[] = {
>   	{ .id = "QCOM8160", .driver_data = 1 },
>   	{}
> @@ -205,8 +255,9 @@ static const struct acpi_device_id __maybe_unused qcom_rng_acpi_match[] = {
>   MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match);
>   
>   static const struct of_device_id __maybe_unused qcom_rng_of_match[] = {
> -	{ .compatible = "qcom,prng", .data = (void *)0},
> -	{ .compatible = "qcom,prng-ee", .data = (void *)1},
> +	{ .compatible = "qcom,prng", .data = &qcom_prng_of_data },
> +	{ .compatible = "qcom,prng-ee", .data = &qcom_prng_ee_of_data },
> +	{ .compatible = "qcom,trng", .data = &qcom_trng_of_data },
>   	{}
>   };
>   MODULE_DEVICE_TABLE(of, qcom_rng_of_match);
> 

Re: [PATCH v4 3/5] crypto: qcom-rng - Add hw_random interface support

[Herbert Xu]

On Tue, Oct 03, 2023 at 09:10:21AM +0200, neil.armstrong@linaro.org wrote:
>
> @@ -198,6 +233,21 @@ static int qcom_rng_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +struct qcom_rng_of_data qcom_prng_of_data = {
> +	.skip_init = false,
> +	.hwrng_support = false,
> +};
> +
> +struct qcom_rng_of_data qcom_prng_ee_of_data = {
> +	.skip_init = true,
> +	.hwrng_support = false,
> +};
> +
> +struct qcom_rng_of_data qcom_trng_of_data = {
> +	.skip_init = true,
> +	.hwrng_support = true,
> +};
> +

I've added static to these three.  Please build your patches
with C=1 W=1 in future.

Thanks,
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [PATCH v4 0/5] arm64: qcom: sm8x50: enable RNG

[Herbert Xu]

On Tue, Oct 03, 2023 at 09:10:18AM +0200, Neil Armstrong wrote:
> Enable RNG on SM8550 & SM8450 by reverting the PRNG bindings & DT
> for SM8450 and correctly document it as a True Random Number Generator.
> 
> - SM8550 QRD test run:
> 
> smccc_trng qcom_hwrng 
> 
> qcom_hwrng
> 
> rngtest 6.15
> Copyright (c) 2004 by Henrique de Moraes Holschuh
> This is free software; see the source for copying conditions.  There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
> 
> rngtest: starting FIPS tests...
> rngtest: bits received from input: 209420032
> rngtest: FIPS 140-2 successes: 10461
> rngtest: FIPS 140-2 failures: 10
> rngtest: FIPS 140-2(2001-10-10) Monobit: 1
> rngtest: FIPS 140-2(2001-10-10) Poker: 2
> rngtest: FIPS 140-2(2001-10-10) Runs: 3
> rngtest: FIPS 140-2(2001-10-10) Long run: 4
> rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
> rngtest: input channel speed: (min=9.219; avg=63.879; max=19073.486)Mibits/s
> rngtest: FIPS tests speed: (min=24.965; avg=29.093; max=118.469)Mibits/s
> rngtest: Program run time: 10002827 microseconds
> 
> - SM8450 HDK test run:
> 
> qcom_hwrng
> 
> rngtest 6.15
> Copyright (c) 2004 by Henrique de Moraes Holschuh
> This is free software; see the source for copying conditions.  There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
> 
> rngtest: starting FIPS tests...
> rngtest: bits received from input: 420580032
> rngtest: FIPS 140-2 successes: 21014
> rngtest: FIPS 140-2 failures: 15
> rngtest: FIPS 140-2(2001-10-10) Monobit: 2
> rngtest: FIPS 140-2(2001-10-10) Poker: 0
> rngtest: FIPS 140-2(2001-10-10) Runs: 7
> rngtest: FIPS 140-2(2001-10-10) Long run: 6
> rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
> rngtest: input channel speed: (min=15.711; avg=50.033; max=32.493)Mibits/s
> rngtest: FIPS tests speed: (min=136.239; avg=203.833; max=227.065)Mibits/s
> rngtest: Program run time: 10000978 microseconds
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> Changes in v4:
> - changed to an enum in first bindings patch to simplify sm8550 change
> - integrate Om's patch from (https://lore.kernel.org/all/20230926102005.3277045-1-quic_omprsing@quicinc.com)
>   to simplify maintainer's life
> - rebased on next-20230929
> - dropped already applied revert
> - Link to v3: https://lore.kernel.org/r/20230828-topic-sm8550-rng-v3-0-7a0678ca7988@linaro.org
> 
> Changes in v3:
> - Removed invalid character in commit msg
> - Added review tags
> - Removed applied patch 1
> - Link to v2: https://lore.kernel.org/r/20230824-topic-sm8550-rng-v2-0-dfcafbb16a3e@linaro.org
> 
> Changes in v2:
> - Revert SM8450 DT & bindings
> - Add new qcom,trng compatible and use it for SM8450 & SM8550
> - Explicitly didn't collect the Reviewed-by tags due to the compatible change
> - Link to v1: https://lore.kernel.org/r/20230822-topic-sm8550-rng-v1-0-8e10055165d1@linaro.org
> 
> ---
> Neil Armstrong (4):
>       dt-bindings: crypto: qcom,prng: document that RNG on SM8450 is a TRNG
>       dt-bindings: crypto: qcom,prng: document SM8550
>       arm64: dts: qcom: sm8550: add TRNG node
>       arm64: dts: qcom: sm8450: add TRNG node
> 
> Om Prakash Singh (1):
>       crypto: qcom-rng - Add hw_random interface support
> 
>  .../devicetree/bindings/crypto/qcom,prng.yaml      | 26 +++++++--
>  arch/arm64/boot/dts/qcom/sm8450.dtsi               |  5 ++
>  arch/arm64/boot/dts/qcom/sm8550.dtsi               |  5 ++
>  drivers/crypto/qcom-rng.c                          | 65 +++++++++++++++++++---
>  4 files changed, 89 insertions(+), 12 deletions(-)
> ---
> base-commit: df964ce9ef9fea10cf131bf6bad8658fde7956f6
> change-id: 20230822-topic-sm8550-rng-c83142783e20

Patches 1-3 applied.  Thanks.
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: (subset) [PATCH v4 0/5] arm64: qcom: sm8x50: enable RNG

[Bjorn Andersson]

On Tue, 03 Oct 2023 09:10:18 +0200, Neil Armstrong wrote:
> Enable RNG on SM8550 & SM8450 by reverting the PRNG bindings & DT
> for SM8450 and correctly document it as a True Random Number Generator.
> 
> - SM8550 QRD test run:
> 
> smccc_trng qcom_hwrng
> 
> [...]

Applied, thanks!

[4/5] arm64: dts: qcom: sm8550: add TRNG node
      commit: 3b3ba999046e246cfd570e5399adea2f82df9312
[5/5] arm64: dts: qcom: sm8450: add TRNG node
      commit: c2c9fa136253daf6b3e25c3ea4952d9f2c4da8cf

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>