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([2001:a61:34c9:ea01:14b4:7ed9:5135:9381]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56eb0bsm19864735e9.22.2024.10.15.07.51.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 07:51:05 -0700 (PDT) Message-ID: <35d247418b8bd43695644f395901b117a1014109.camel@gmail.com> Subject: Re: [PATCH v6 2/8] dt-bindings: iio: dac: adi-axi-dac: add ad3552r axi variant From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Angelo Dureghello Cc: Nuno =?ISO-8859-1?Q?S=E1?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Date: Tue, 15 Oct 2024 16:51:04 +0200 In-Reply-To: <776ed45e-7ca8-42e8-9050-86928f223965@baylibre.com> References: <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-0-eeef0c1e0e56@baylibre.com> <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-2-eeef0c1e0e56@baylibre.com> <776ed45e-7ca8-42e8-9050-86928f223965@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-1.fc40) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2024-10-15 at 09:40 -0500, David Lechner wrote: > On 10/15/24 2:44 AM, Angelo Dureghello wrote: > > On 14.10.2024 16:13, David Lechner wrote: > > > On 10/14/24 5:08 AM, Angelo Dureghello wrote: > > > > From: Angelo Dureghello > > > >=20 > > > > Add a new compatible and related bindigns for the fpga-based > > > > "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. > > > >=20 > > > > The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the > > > > generic AXI "DAC" IP, intended to control ad3552r and similar chips= , > > > > mainly to reach high speed transfer rates using a QSPI DDR > > > > (dobule-data-rate) interface. > > > >=20 > > > > The ad3552r device is defined as a child of the AXI DAC, that in > > > > this case is acting as an SPI controller. > > > >=20 > > > > Note, #io-backend is present because it is possible (in theory anyw= ay) > > > > to use a separate controller for the control path than that used > > > > for the datapath. > > > >=20 > > > > Signed-off-by: Angelo Dureghello > > > > --- > > > > =C2=A0.../devicetree/bindings/iio/dac/adi,axi-dac.yaml=C2=A0=C2=A0 = | 56 > > > > ++++++++++++++++++++-- > > > > =C2=A01 file changed, 53 insertions(+), 3 deletions(-) > > > >=20 > > > > diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.= yaml > > > > b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > > index a55e9bfc66d7..2b7e16717219 100644 > > > > --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > > +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > > @@ -19,11 +19,13 @@ description: | > > > > =C2=A0=C2=A0 memory via DMA into the DAC. > > > > =C2=A0 > > > > =C2=A0=C2=A0 https://wiki.analog.com/resources/fpga/docs/axi_dac_ip > > > > +=C2=A0 https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/= index.html > > > > =C2=A0 > > > > =C2=A0properties: > > > > =C2=A0=C2=A0 compatible: > > > > =C2=A0=C2=A0=C2=A0=C2=A0 enum: > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,axi-dac-9.1.b > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,axi-ad3552r > > > > =C2=A0 > > > > =C2=A0=C2=A0 reg: > > > > =C2=A0=C2=A0=C2=A0=C2=A0 maxItems: 1 > > > > @@ -36,7 +38,14 @@ properties: > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - const: tx > > > > =C2=A0 > > > > =C2=A0=C2=A0 clocks: > > > > -=C2=A0=C2=A0=C2=A0 maxItems: 1 > > > > +=C2=A0=C2=A0=C2=A0 minItems: 1 > > > > +=C2=A0=C2=A0=C2=A0 maxItems: 2 > > > > + > > > > +=C2=A0 clock-names: > > > > +=C2=A0=C2=A0=C2=A0 minItems: 1 > > > > +=C2=A0=C2=A0=C2=A0 items: > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - const: s_axi_aclk > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - const: dac_clk > > > > =C2=A0 > > > > =C2=A0=C2=A0 '#io-backend-cells': > > > > =C2=A0=C2=A0=C2=A0=C2=A0 const: 0 > > > > @@ -47,7 +56,16 @@ required: > > > > =C2=A0=C2=A0 - reg > > > > =C2=A0=C2=A0 - clocks > > > > =C2=A0 > > > > -additionalProperties: false > > > > +allOf: > > > > +=C2=A0 - if: > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 properties: > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 compatible: > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 contains: > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= const: adi,axi-ad3552r > > > > +=C2=A0=C2=A0=C2=A0 then: > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 $ref: /schemas/spi/spi-controller.y= aml# > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 properties: > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clocks: > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 minIte= ms: 2 > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clock-names: > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 minIte= ms: 2 > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 required: > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clock-names > > > =C2=A0 +=C2=A0=C2=A0=C2=A0 else: > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 properties: > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clocks: > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 maxIte= ms: 1 > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clock-names: > > > =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 maxIte= ms: 1 > > >=20 > > > We could make the checking of clocks more strict to show > > > the intent: > > >=20 > > > adi,axi-dac-9.1.b only has 1 clock and clock-names is optional. > > >=20 > > > adi,axi-ad3552r always has 2 clocks and clock-names is required. > > >=20 > > is this really necessary ? At v.6 would not fix things > > not reallyh necessary. > > =C2=A0 > It is just a suggestion from me. I will leave it to the maintainers > to say if it is necessary or not. (If they don't say anything, then > we'll take it to mean it isn't necessary.) >=20 Not a DT maintainer but IMHO, having these kind of checks in the bindings i= s very useful. - Nuno S=C3=A1