Re: [PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock

[Jie Luo <quic_luoj@quicinc.com>]

On 5/2/2025 11:53 PM, George Moussalem wrote:
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55- 
>>> v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>>> index 
>>> 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a185437886b04b0d99e8e 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>>> +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>>> @@ -124,5 +124,6 @@ uart_pins: uart-pins-state {
>>>   };
>>>   &xo_board_clk {
>>> -    clock-frequency = <24000000>;
>>> +    clock-div = <4>;
>>> +    clock-mult = <1>;
>>>   };
>>
>> Is the divider a part of the SoC? If so, please move these values to 
>> the SoC dtsi file.
> 
> my 'best guess' is that the ref clk for ipq5018 is always 96MHZ and the 
> XO board clk is 24MHZ, so it should be safe to move it to the dtsi, but 
> this is purely based on the 5 different board types I have.
> 
> @Luo Jie: can you confirm the above?

The xo_board_clk is achieved by the bootstrap PINs, which should be
always 24 MHZ, we can move it to the RDP common DTSI if it is existed.