Re: [PATCH v2 0/2] drm: bridge: ti-sn65dsi83: Improve dual-link LVDS support

Alexander Stein
2026-03-24T11:11:05Z

Am Dienstag, 24. März 2026, 12:00:43 CET schrieb tessolveupstream@gmail.com:
> [snip]
> > Thanks for the detailed explanation.
> Regarding the panel timings, they are not explicitly defined in the DTS.
> The panel is currently using the timings provided by the panel driver
> (panel-simple.c), specifically:
>
> static const struct display_timing auo_g133han01_timings = {
> .pixelclock = { 134000000, 141200000, 149000000 },
> .hactive = { 1920, 1920, 1920 },
> .hfront_porch = { 39, 58, 77 },
> .hback_porch = { 59, 88, 117 },
> .hsync_len = { 28, 42, 56 },
> .vactive = { 1080, 1080, 1080 },
> .vfront_porch = { 3, 8, 11 },
> .vback_porch = { 5, 14, 19 },
> .vsync_len = { 4, 14, 19 },
> };
>
> The panel I am using is based on AUO G133HAN01, and the datasheet can
> be found here:
> https://datasheet4u.com/pdf/1257948/G133HAN01.0.pdf > About CHA_DSI_CLK_RANGE: what is your DSI clock?
> >
>
> In the current working configuration, the measured clock frequencies
> are:
> DSI_CLK: ~422MHz
> LVDS_CLK(both A & B Channels): ~70MHz
> > Finally I don't think the swing values are problematic, so I'd leave them
> > as the last thing to check.

I managed to get this display running with this DSI->LVDS bridge on
TQMa8MxML/TQMa8MxNL (imx8mm or imx8mn) platform.
See [1] for the DT. What platform/ DSI host are you using?

Best regards,
Alexander

[1] https://lore.kernel.org/all/20260316135820.760073-2-alexander.stein@ew.tq-group.com/
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider