Re: [PATCH v2 0/2] drm: bridge: ti-sn65dsi83: Improve dual-link LVDS support

tessolveupstream
2026-03-12T12:34:55Z

On 12-03-2026 10:35, Marek Vasut wrote:
> On 3/12/26 5:37 AM, Sudarshan Shetty wrote:
>> Hi all,
>>
>> This patch series improves dual-link LVDS support in the SN65DSI83
>> DSI-to-LVDS bridge driver.
>>
>> Currently the driver programs identical horizontal timing parameters
>> for both single-link and dual-link LVDS modes. According to TI
>> documentation, when operating in dual-link mode the horizontal timing
>> values must be divided by two before being programmed into the device.
>> Without this adjustment, some panels fail to light up or produce
>> corrupted output.
>>
>> TI also provides recommended register settings for dual-link LVDS
>> operation. This series adds support for an optional DT property
>> ti,dual-link-video-mode that enables the required configuration
>> in the driver.
>>
>> When the property is present, the driver applies the recommended
>> register settings and uses a simplified DSI video mode configuration
>> to ensure correct dual-link LVDS operation.
>>
>> Summary:
>>   - Add DT binding for ti,dual-link-video-mode
>>   - Add driver support to enable dual-link LVDS configuration
>>   - Apply recommended register settings for dual-link operation
>>   - Adjust DSI mode flags when dual-link mode is enabled
>>
>> Changes in v2:
>>   - Introduce ti,dual-link-video-mode DT property
>>   - Add DT binding documentation for the new property
>>   - Update driver to read the DT property and apply dual-link
>>     configuration conditionally
>>   - Adjust DSI mode flags when dual-link video mode is enabled
>>   - Update commit messages
>>
>> Thanks,
>> Anusha
>>
>> Sudarshan Shetty (2):
>>    dt-bindings: display: bridge: ti,sn65dsi83: Add dual-link video mode
>>      property
>>    drm: bridge: ti-sn65dsi83: Add support for dual-link LVDS video mode
>>
>>   .../bindings/display/bridge/ti,sn65dsi83.yaml |  9 ++++
>>   drivers/gpu/drm/bridge/ti-sn65dsi83.c         | 52 +++++++++++++++++--
>>   2 files changed, 57 insertions(+), 4 deletions(-)
> +CC Luca
>
> You might want to look at recently posted:
>
> [PATCH 2/3] drm/bridge: ti-sn65dsi83: halve horizontal syncs for dual LVDS output

Thanks for pointing this out.
I tried applying the patch “[PATCH 2/3] drm/bridge: ti-sn65dsi83: halve horizontal syncs for dual LVDS output” on top of the current tree and
removed the changes that I had previously added in the driver.
However, with this patch applied, I am currently seeing only the backlight turning on and no image on the LVDS panel.
For reference, the LVDS panel used on our platform is G133HAN01.1 and the
DSI-to-dual-link LVDS bridge is SN65DSI84ZXHR.

During our earlier debugging, we went through several trial-and-error
iterations and also received support from TI. According to TI, when
operating in dual-link mode the horizontal timing parameters must be
divided by two before being written to the device. Without this
adjustment, the panel either does not light up or shows corrupted output.

TI also shared a set of recommended register settings for dual-link mode,
which were derived using the TI DSI-Tuner tool. These settings helped us
get the panel working on our hardware during testing.
For reference, the register configuration suggested by TI is as follows:

regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 0x05);
regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
regmap_write(ctx->regmap, REG_DSI_CLK, 0x53);
regmap_write(ctx->regmap, REG_LVDS_FMT, 0x6f);
regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x00);
regmap_write(ctx->regmap,
REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 0x00);
regmap_write(ctx->regmap,
REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH, 0x00);
regmap_write(ctx->regmap,
REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 0x10);
regmap_write(ctx->regmap,
REG_VID_CHA_HORIZONTAL_BACK_PORCH, 0x28);
regmap_write(ctx->regmap,
REG_VID_CHA_VERTICAL_BACK_PORCH, 0x00);
regmap_write(ctx->regmap,
REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 0x00);
regmap_write(ctx->regmap,
REG_VID_CHA_VERTICAL_FRONT_PORCH, 0x00);

If it would help, we can test any proposed changes on our hardware.
Please let me know if incorporating these register settings or additional adjustments would be the right direction for supporting dual-link LVDS
in this driver.
Is the current patch expected to fully support dual-link LVDS, or are
there additional changes planned for the SN65DSI84 driver?