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From: Mikko Perttunen <cyndis@kapsi.fi>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Alexandre Courbot <gnurou@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Rhyland Klein <rklein@nvidia.com>,
	linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 7/7] clk: tegra: fix type for m field
Date: Thu, 23 Feb 2017 11:18:16 +0200	[thread overview]
Message-ID: <35f5417f-fd92-706c-192b-037819a1661d@kapsi.fi> (raw)
In-Reply-To: <1487776444-4701-8-git-send-email-pdeschrijver@nvidia.com>

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

On 22.02.2017 17:14, Peter De Schrijver wrote:
> When used as part of fractional ndiv calculations, the current range is not
> enough because the denominator of the fraction is multiplied with m.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/clk.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 6ba82ec..a62ea73 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -116,7 +116,7 @@ struct tegra_clk_pll_freq_table {
>  	unsigned long	input_rate;
>  	unsigned long	output_rate;
>  	u32		n;
> -	u16		m;
> +	u32		m;
>  	u8		p;
>  	u8		cpcon;
>  	u16		sdm_data;
>

      reply	other threads:[~2017-02-23  9:18 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-22 15:13 [PATCH 0/7] Tegra210 clock bug fixes Peter De Schrijver
     [not found] ` <1487776444-4701-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-02-22 15:13   ` [PATCH 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1 Peter De Schrijver
     [not found]     ` <1487776444-4701-2-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-02-22 16:38       ` Mikko Perttunen
2017-02-22 15:14   ` [PATCH 5/7] clk: tegra: don't warn for PLL defaults unnecessarily Peter De Schrijver
2017-02-23  9:06     ` Mikko Perttunen
2017-02-22 15:13 ` [PATCH 2/7] clk: tegra: fix isp clock modelling Peter De Schrijver
2017-02-23  7:49   ` Mikko Perttunen
2017-02-22 15:13 ` [PATCH 3/7] clk: tegra: correct afi parent Peter De Schrijver
     [not found]   ` <1487776444-4701-4-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-02-23  9:01     ` Mikko Perttunen
2017-02-22 15:13 ` [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock Peter De Schrijver
     [not found]   ` <1487776444-4701-5-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-02-22 16:31     ` Mikko Perttunen
2017-02-23  8:17   ` Mikko Perttunen
     [not found]     ` <3be69e34-354c-81ea-0c5e-182a79aa42d0-/1wQRMveznE@public.gmane.org>
2017-02-23  8:17       ` Mikko Perttunen
2017-02-22 15:14 ` [PATCH 6/7] clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation Peter De Schrijver
     [not found]   ` <1487776444-4701-7-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-02-23  9:18     ` Mikko Perttunen
2017-02-22 15:14 ` [PATCH 7/7] clk: tegra: fix type for m field Peter De Schrijver
2017-02-23  9:18   ` Mikko Perttunen [this message]

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