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I haven't fully understood some of the details yet, I'll do my best to work through them. Thanks again for your reminder. On 10/10/2025 10:42 AM, Krzysztof Kozlowski wrote: > [ EXTERNAL EMAIL ] > > On 10/10/2025 04:38, Chuan Liu wrote: >> Hi Jerome, >> >> >> On 10/9/2025 3:59 PM, Jerome Brunet wrote: >>> [ EXTERNAL EMAIL ] >>> >>> On Thu 09 Oct 2025 at 11:09, Chuan Liu wrote: >>> >>>> Hi Jerome, >>>> >>>> Thanks for your review, because the national day holidays did not >>>> timely feedback. >>>> >>>> >>>> On 10/1/2025 3:45 PM, Jerome Brunet wrote: >>>>> [ EXTERNAL EMAIL ] >>>>> >>>>> On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay >>>>> wrote: >>>>> >>>>>> This patch series includes changes related to the PLL and peripheral >>>>>> clocks for both the A4 and A5 SoCs. >>>>>> >>>>>> The patches for A5 were previously submitted up to V3 by Xianwei. >>>>>> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/ >>>>>> After friendly coordination, I’ve taken over and continued the >>>>>> submission as part of this series. The dt-bindings patch retains Rob's >>>>>> original "Reviewed-by" tag, and I hope this hasn’t caused any >>>>>> additional confusion. >>>>> ... and yet you restart the versioning of the series making it harder >>>>> for people to follow that >>>> >>>> Sorry for the inconvenience caused. The main changes compared to the >>>> previous version by Xianwei are in the driver part. >>>> >>>> The dt-bindings part only has minor modifications in [PATCH 14/19]. >>>> >>>> The driver part has relatively larger changes because it needs to be >>>> based on the code base you previously submitted. >>> I'm not seeing a justification for the mess introduced and I'm not >>> looking for one to be honest >> >> >> Previously, I provided a basic version of the A5 clock driver to >> Xianwei, and he helped improve it before submitting it. >> >> Xianwei has been responsible for upstreaming many of our modules. >> Since clock drivers require significant effort, I’m sharing the >> workload by submitting some of the clock-related patches. >> >> The three versions previously submitted by Xianwei mainly focused on >> improving the dt-bindings based on Rob’s feedback. The driver part >> remained unchanged. >> >> The driver part in my current patch series has undergone relatively >> large modifications to adapt to the latest code base, so comparing it >> to the previous versions may not be very meaningful. >> >> If it's more appropriate for the A5 clock-related patches to continue >> evolving based on Xianwei's earlier v3 series, please feel free to >> point it out. I will continue to assist Xianwei in completing the >> submission of the remaining A5 clock patches. >> >> >>>>>> Both A4 and A5 belong to the Audio series. Judging by their names, one >>>>>> might assume that A5 is an upgrade to A4, but in fact, A5 was released >>>>>> a year earlier than A4. >>>>>> >>>>>> Since there are differences in the PLLs and peripheral clocks between >>>>>> the A4 and A5 SoCs (especially the PLL), and taking into account factors >>>>>> such as memory footprint and maintainability, this series does not >>>>>> attempt to merge the two into a shared driver as was done for >>>>>> G12A/G12B/SM1. >>>>> ... and we end up with 19 patches series while it could be splitted into >>>>> manageable series, for each controller of each SoC >>>> >>>> I'm not sure if I understood you correctly. >>>> >>>> Do you mean that I should split this series of 19 patches into multiple >>>> patch series and send them separately? For example: >>>> serie 1: A4 SCMI clock controller (dt-bindings) >>>> serie 2: A4 PLL clock controller (dt-bindings, driver, dts) >>>> serie 3: A4 peripherals clock controller (dt-bindings, driver, dts) >>>> ... A5 similarly? >>> Things that do not actually depends on each other or which are not >>> merged through the same tree should not be sent together. There is >>> nothing new here. Same basic reminders on each submission. >> >> >> Sorry, but I'm still not quite sure if I understood you correctly. >> >> This series of 19 patches mainly falls into three major categories: >> * Optimize PLL driver >> * PLLs and peripherals for A4 >> * PLLs and peripherals for A5 >> >> Are you suggesting that the PLL driver part should be sent as a >> separate patch series, while the A4 and A5 parts should still follow >> the previous A5/C3-style submission? >> > > Please read submitting patches, soc maintainer profile and DT submitting > patches documents. You ask us to repeat same knowledge multiple times. > It's waste of our time, so we have documented it for your convenience. > > Best regards, > Krzysztof