From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sergei Shtylyov Subject: [PATCH v2 2/3] ARM: dts: blanche: add SCIF0/3 pins Date: Mon, 04 Jul 2016 23:54:04 +0300 Message-ID: <3636132.pRUtqSxpmQ@wasted.cogentembedded.com> References: <2793535.9X0Tq7I1Mq@wasted.cogentembedded.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: In-Reply-To: <2793535.9X0Tq7I1Mq@wasted.cogentembedded.com> Sender: linux-renesas-soc-owner@vger.kernel.org To: horms@verge.net.au, linux-renesas-soc@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: magnus.damm@gmail.com, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Add the (previously omitted) SCIF0/3 pin data to the Blanche board's device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 2: - added Geert's tag. arch/arm/boot/dts/r8a7792-blanche.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7792-blanche.dts =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7792-blanche.dts +++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts @@ -57,10 +57,28 @@ clock-frequency = <20000000>; }; +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif3_pins: scif3 { + groups = "scif3_data"; + function = "scif3"; + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; }; &scif3 { + pinctrl-0 = <&scif3_pins>; + pinctrl-names = "default"; + status = "okay"; };