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(dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id m9-20020a195209000000b004f86943d11fsm1105226lfb.49.2023.06.26.06.37.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Jun 2023 06:37:33 -0700 (PDT) Message-ID: <363c3902-a91a-a3a1-b721-65c10ac88421@linaro.org> Date: Mon, 26 Jun 2023 16:37:33 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2 04/26] dt-bindings: clock: qcom,krait-cc: Krait core clock controller Content-Language: en-GB To: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold References: <20230625202547.174647-1-dmitry.baryshkov@linaro.org> <20230625202547.174647-5-dmitry.baryshkov@linaro.org> <40e70fff-88dc-683e-0016-1a24389b75b8@linaro.org> From: Dmitry Baryshkov In-Reply-To: <40e70fff-88dc-683e-0016-1a24389b75b8@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 26/06/2023 14:21, Konrad Dybcio wrote: > On 25.06.2023 22:25, Dmitry Baryshkov wrote: >> Define bindings for the Qualcomm Krait CPU and L2 clock controller. This >> device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up >> to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is >> represented as the interconnect to facilitate L2 frequency scaling >> together with scaling the CPU frequencies. >> >> Signed-off-by: Dmitry Baryshkov >> --- > Worth noting that there's no Krait cluster containing more than 4 > cores and the last SoC using this uarch was released 10y ago, so > we can quite confidently say that the max cpu no won't change. Yep. It it were new bindings, I'd probably use a different order: L2, then CPUs. But here I'm just documenting what is already done by the driver. > > Konrad >> include/dt-bindings/clock/qcom,krait-cc.h | 17 +++++++++++++++++ >> 1 file changed, 17 insertions(+) >> create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h >> >> diff --git a/include/dt-bindings/clock/qcom,krait-cc.h b/include/dt-bindings/clock/qcom,krait-cc.h >> new file mode 100644 >> index 000000000000..ff69a0a968d8 >> --- /dev/null >> +++ b/include/dt-bindings/clock/qcom,krait-cc.h >> @@ -0,0 +1,17 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> +/* >> + * Copyright (C) 2023 Linaro Ltd. All rights reserved. >> + */ >> + >> +#ifndef __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H >> +#define __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H >> + >> +#define KRAIT_CPU_0 0 >> +#define KRAIT_CPU_1 1 >> +#define KRAIT_CPU_2 2 >> +#define KRAIT_CPU_3 3 >> +#define KRAIT_L2 4 >> + >> +#define KRAIT_NUM_CLOCKS 5 >> + >> +#endif -- With best wishes Dmitry