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[178.79.73.218]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6433a4b1fadsm8008375a12.31.2025.11.16.04.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Nov 2025 04:10:37 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Krzysztof Kozlowski Cc: wens@csie.org, samuel@sholland.org, mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH 4/7] dt-bindings: display: allwinner: Add DE33 planes Date: Sun, 16 Nov 2025 13:10:35 +0100 Message-ID: <3659815.iIbC2pHGDl@jernej-laptop> In-Reply-To: References: <20251115141347.13087-1-jernej.skrabec@gmail.com> <4691137.LvFx2qVVIh@jernej-laptop> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne nedelja, 16. november 2025 ob 12:49:45 Srednjeevropski standardni =C4= =8Das je Krzysztof Kozlowski napisal(a): > On 16/11/2025 12:44, Jernej =C5=A0krabec wrote: > > Hi! > >=20 > > Dne nedelja, 16. november 2025 ob 12:29:27 Srednjeevropski standardni = =C4=8Das je Krzysztof Kozlowski napisal(a): > >> On Sat, Nov 15, 2025 at 03:13:44PM +0100, Jernej Skrabec wrote: > >>> Allwinner Display Engine 3.3 contains planes, which are shared resour= ces > >>> between all mixers present in SoC. They can be assigned to specific > >>> mixer by using registers which reside in display clocks MMIO. > >>> > >>> Add a binding for them. > >>> > >>> Signed-off-by: Jernej Skrabec > >>> --- > >>> .../allwinner,sun50i-h616-de33-planes.yaml | 44 +++++++++++++++++= ++ > >>> 1 file changed, 44 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/display/allwinn= er,sun50i-h616-de33-planes.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/display/allwinner,sun5= 0i-h616-de33-planes.yaml b/Documentation/devicetree/bindings/display/allwin= ner,sun50i-h616-de33-planes.yaml > >>> new file mode 100644 > >>> index 000000000000..801e5068a6b5 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/display/allwinner,sun50i-h616= =2Dde33-planes.yaml > >>> @@ -0,0 +1,44 @@ > >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > >>> +%YAML 1.2 > >>> +--- > >>> +$id: http://devicetree.org/schemas/display/allwinner,sun50i-h616-de3= 3-planes.yaml# > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>> + > >>> +title: Allwinner H616 Display Engine 3.3 planes > >>> + > >>> +maintainers: > >>> + - Jernej Skrabec > >>> + > >>> +description: | > >> > >> Do not need '|' unless you need to preserve formatting. > >> > >>> + Display Engine 3.3 planes are independent of mixers, contrary to > >>> + previous generations of Display Engine. Planes can be assigned to > >>> + mixers independently and even dynamically during runtime. > >>> + > >>> +properties: > >>> + compatible: > >>> + enum: > >>> + - allwinner,sun50i-h616-de33-planes > >>> + > >>> + reg: > >>> + maxItems: 1 > >>> + > >>> + allwinner,plane-mapping: > >>> + $ref: /schemas/types.yaml#/definitions/phandle > >>> + description: Phandle of Display Engine clock node > >> > >> You description is almost duplicating property name. You need to expla= in > >> here how this device uses them. > >=20 > > So I guess I can copy commit description here? It is needed to > > access registers from different core, so it can assign (map) > > planes between mixers at runtime. >=20 >=20 > "to assign (map) planes between mixers." is enough. >=20 > But it looks unfortunately like a spaghetti. >=20 > Your mixer binding references via phandle this planes. These planes > reference via phandle some other region to configure planes between mixer= s. >=20 > Isn't this the job of this device? It is a bit confusing, yes. There is no clean split in register space for some functionality. Register space for this node on H616 SoC represents 6 planes (each plane consist of framebuffer management, CSC unit, scaler, etc.) but not actual registers which tell to which mixer they are currently assigned. Best regards, Jernej