Re: [PATCH net-next 09/12] gpio: tc956x: add TC956x/QPS615 support

[Andrew Lunn <andrew@lunn.ch>]

On Sat, May 02, 2026 at 08:45:48PM -0500, Alex Elder wrote:
> On 5/1/26 1:36 PM, Andrew Lunn wrote:
> > > + * There is a TC956X PCI power controller driver that accesses the
> > > + * direction and output value registers for GPIOs 2 and 3.  These
> > > + * GPIOs control the reset signal for the two downstream PCIe ports.
> > > + * Their values will never change during operation of this driver, and
> > > + * this driver reserves these two GPIOS.
> > 
> > Why doesn't this power controller driver actually use this driver to
> > control the GPIOs? Chicken/egg?
> 
> I am not the one with authority on this, but yes, that's my
> understanding.  *Something* about this chip requires that the
> PCIe ports need to have some configuration done on them *before*
> PCIe is powered up.  So that driver uses the I2C interface to
> apply these settings.  Meanwhile this driver uses the PCIe-mapped
> memory to manage the GPIO registers.

The diagram you have is:


              ----------------------------------
              |              Host              |
              ------+...+----------+........+---
                    |i2c|          |  PCIe  |
    ----------------+...+----------+........+------
    | TC956x        |I2C|          |upstream|     |
    |               -----        --+--------+---  |
    |  -----  ------  -------    | PCIe switch |  |
    |  |SPI|  |GPIO|  |reset|    |             |  |
    |  -----  ------  |clock|    | DS3 DS2 DS1 |  |
    |                 -------    ---++--++--++--  |
    |  -----  ------     downstream//    \\  \\   |  downstream
    |  |MCU|  |SRAM|    /==========/      \\  \===== PCIe port 1
    |  -----  ------   //PCIe port 3       \\     |
    |                  ||                   \======= downstream
    |  ----+-----------++-----------+----         |  PCIe port 2
    |  | M | internal PCIe endpoint | M |         |
    |  | S |------------------------| S |  ------ |
    |  | I |   PCIe   |  |   PCIe   | I |  |UART| |
    |  | G |function 0|  |function 1| G |  ------ |
    |  | E |----++----|  |----++----| E |         |
    |  | N |  eMAC 0  |  |  eMAC 1  | N |         |
    --------+.......+------+.....+-----------------
            |USXGMII|      |SGMII|
          --+.......+--  --+.....+--
          |  ARQ113C  |  | QEP8121 |
          |    PHY    |  |   PHY   |
          -------------  -----------

The two Ethernet controllers are hanging off port 3 of the
switch. However, the GPIO block is just floating in space. What
address space is it in?

I'm wondering if the GPIO controller should be a device/driver of its
own? It probes first. The PCI power controller driver then probes, and
has phandles to the GPIO controller so it can activate ports 1 and
2. Parallel to that the Ethernet driver(s) can probe, also using
phandles to the GPIO they need.

Looking at this diagram, putting the GPIO controller within one of the
port 3 functions is wrong. But maybe the diagram is not accurate.

     Andrew