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[98.34.199.138]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7dc975b057bsm7891589a34.20.2026.04.19.15.38.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Apr 2026 15:38:25 -0700 (PDT) From: "Alex G." To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan Cc: sumit.garg@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, Varadarajan Narayanan , Konrad Dybcio Subject: Re: [PATCH v4 1/4] arm64: dts: qcom: ipq9574: Add gpio details for eMMC Date: Sun, 19 Apr 2026 17:38:24 -0500 Message-ID: <3675281.vFx2qVVIhK@nukework.gtech> In-Reply-To: <20260202073322.259534-2-varadarajan.narayanan@oss.qualcomm.com> References: <20260202073322.259534-1-varadarajan.narayanan@oss.qualcomm.com> <20260202073322.259534-2-varadarajan.narayanan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Monday, February 2, 2026 1:33:19=E2=80=AFAM Central Daylight Time Varada= rajan=20 Narayanan wrote: Hi Varadarajan, > The RDP433 has NAND and eMMC variants. Presently, only NAND variant is > supported. To enable support for eMMC variant, add the relevant GPIO > related information. >=20 > Do not enable NAND by default here. Enable it in board specific DTS. >=20 This commit references sdc_default_state in the .dtsi file, without definin= g it.=20 It creates a silent dependency on the board .dts, who must now define the p= ins.=20 This makes no sense to me for boards that don't have eMMC. As an example, i= t=20 breaks most downstream OpenWRT boards. Was this new dependency accidental? Alex > Reviewed-by: Konrad Dybcio > Signed-off-by: Varadarajan Narayanan > --- > v4: Move sdhc properties from emmc dts to SoC dtsi >=20 > v3: Disable nand in ipq9574-rdp-common.dtsi and enable it where required. > Add 'Reviewed-by: Konrad Dybcio' > --- > .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 32 +++++++++++++++++++ > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 9 ++++++ > 2 files changed, 41 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi > b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index > bdb396afb992..e4ae79b2fcd9 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi > @@ -169,6 +169,38 @@ data-pins { > bias-disable; > }; > }; > + > + sdc_default_state: sdc-default-state { > + clk-pins { > + pins =3D "gpio5"; > + function =3D "sdc_clk"; > + drive-strength =3D <8>; > + bias-disable; > + }; > + > + cmd-pins { > + pins =3D "gpio4"; > + function =3D "sdc_cmd"; > + drive-strength =3D <8>; > + bias-pull-up; > + }; > + > + data-pins { > + pins =3D "gpio0", "gpio1", "gpio2", > + "gpio3", "gpio6", "gpio7", > + "gpio8", "gpio9"; > + function =3D "sdc_data"; > + drive-strength =3D <8>; > + bias-pull-up; > + }; > + > + rclk-pins { > + pins =3D "gpio10"; > + function =3D "sdc_rclk"; > + drive-strength =3D <8>; > + bias-pull-down; > + }; > + }; > }; >=20 > &qpic_bam { > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 86c9cb9fffc9..4b8c58982869 > 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -467,6 +467,15 @@ sdhc_1: mmc@7804000 { > clock-names =3D "iface", "core", "xo", "ice"; > non-removable; > supports-cqe; > + pinctrl-0 =3D <&sdc_default_state>; > + pinctrl-names =3D "default"; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; > + mmc-hs400-1_8v; > + mmc-hs400-enhanced-strobe; > + max-frequency =3D <384000000>; > + bus-width =3D <8>; > + > status =3D "disabled"; > };