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Sat, 14 Sep 2024 03:59:32 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48E3xUFo030003 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 14 Sep 2024 03:59:30 GMT Received: from [10.216.29.174] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Sep 2024 20:59:22 -0700 Message-ID: <36bd9f69-e263-08a1-af07-45185ea03671@quicinc.com> Date: Sat, 14 Sep 2024 09:29:17 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v2 0/5] Add support for PCIe3 on x1e80100 Content-Language: en-US To: Qiang Yu , , , , , , , , , , , , , CC: , , , , , , , , , References: <20240913083724.1217691-1-quic_qianyu@quicinc.com> From: Krishna Chaitanya Chundru In-Reply-To: <20240913083724.1217691-1-quic_qianyu@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: zFX8fzgqJUywOZLiwxkJshUCOO-16e_o X-Proofpoint-GUID: zFX8fzgqJUywOZLiwxkJshUCOO-16e_o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 adultscore=0 spamscore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409140026 Hi qiang, In next series can you add logic in controller driver to have new ops for this x1e80100 since this hardware has smmuv3 support but currently the ops_1_9_0 ops which is being used has configuring bdf to sid table which will be not present for this devices. - Krishna Chaitanya. On 9/13/2024 2:07 PM, Qiang Yu wrote: > This series add support for PCIe3 on x1e80100. > > PCIe3 needs additional set of clocks, regulators and new set of PCIe QMP > PHY configuration compare other PCIe instances on x1e80100. Hence add > required resource configuration and usage for PCIe3. > > v2->v1: > 1. Squash [PATCH 1/8], [PATCH 2/8],[PATCH 3/8] into one patch and make the > indentation consistent. > 2. Put dts patch at the end of the patchset. > 3. Put dt-binding patch at the first of the patchset. > 4. Add a new patch where opp-table is added in dt-binding to avoid dtbs > checking error. > 5. Remove GCC_PCIE_3_AUX_CLK, RPMH_CXO_CLK, put in TCSR_PCIE_8L_CLKREF_EN > as ref. > 6. Remove lane_broadcasting. > 7. Add 64 bit bar, Remove GCC_PCIE_3_PIPE_CLK_SRC, > GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK is changed to > GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK. > 8. Add Reviewed-by tag. > 9. Remove [PATCH 7/8], [PATCH 8/8]. > > Qiang Yu (5): > dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 > QMP PCIe PHY Gen4 x8 > dt-bindings: PCI: qcom: Add OPP table for X1E80100 > phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 > clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks > arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 > > .../bindings/pci/qcom,pcie-x1e80100.yaml | 4 + > .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 + > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 202 ++++++++++++++++- > drivers/clk/qcom/gcc-x1e80100.c | 10 +- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 211 ++++++++++++++++++ > .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h | 25 +++ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h | 19 ++ > 7 files changed, 468 insertions(+), 6 deletions(-) > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h >