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([2001:a61:341e:1201:c434:b5b1:98a6:efed]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5c42bb5dd02sm7221881a12.41.2024.09.20.05.47.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 05:47:51 -0700 (PDT) Message-ID: <36e4c636578f2871c0f6b4c6242d71e409215ae0.camel@gmail.com> Subject: Re: [PATCH v3 02/10] dt-bindings: iio: dac: axi-dac: add ad3552r axi variant From: Nuno =?ISO-8859-1?Q?S=E1?= To: Angelo Dureghello , Lars-Peter Clausen , Michael Hennerich , Nuno Sa , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dlechner@baylibre.com Date: Fri, 20 Sep 2024 14:47:50 +0200 In-Reply-To: <20240919-wip-bl-ad3552r-axi-v0-iio-testing-v3-2-a17b9b3d05d9@baylibre.com> References: <20240919-wip-bl-ad3552r-axi-v0-iio-testing-v3-0-a17b9b3d05d9@baylibre.com> <20240919-wip-bl-ad3552r-axi-v0-iio-testing-v3-2-a17b9b3d05d9@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-1.fc40) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2024-09-19 at 11:19 +0200, Angelo Dureghello wrote: > From: Angelo Dureghello >=20 > Add a new compatible and related bindigns for the fpga-based > "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. >=20 > The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the > generic AXI "DAC" IP, intended to control ad3552r and similar chips, > mainly to reach high speed transfer rates using an additional QSPI > DDR interface. >=20 > The ad3552r device is defined as a child of the AXI DAC, that in > this case is acting as an SPI controller. >=20 > Signed-off-by: Angelo Dureghello > --- > =C2=A0.../devicetree/bindings/iio/dac/adi,axi-dac.yaml=C2=A0=C2=A0 | 40 += +++++++++++++++++++-- > =C2=A01 file changed, 37 insertions(+), 3 deletions(-) >=20 > diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > index a55e9bfc66d7..6cf0c2cb84e7 100644 > --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > @@ -19,11 +19,13 @@ description: | > =C2=A0=C2=A0 memory via DMA into the DAC. > =C2=A0 > =C2=A0=C2=A0 https://wiki.analog.com/resources/fpga/docs/axi_dac_ip > +=C2=A0 https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.= html > =C2=A0 > =C2=A0properties: > =C2=A0=C2=A0 compatible: > =C2=A0=C2=A0=C2=A0=C2=A0 enum: > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,axi-dac-9.1.b > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - adi,axi-ad3552r > =C2=A0 > =C2=A0=C2=A0 reg: > =C2=A0=C2=A0=C2=A0=C2=A0 maxItems: 1 > @@ -41,22 +43,54 @@ properties: > =C2=A0=C2=A0 '#io-backend-cells': > =C2=A0=C2=A0=C2=A0=C2=A0 const: 0 > =C2=A0 > +=C2=A0 '#address-cells': > +=C2=A0=C2=A0=C2=A0 const: 1 > + > +=C2=A0 '#size-cells': > +=C2=A0=C2=A0=C2=A0 const: 0 > + > =C2=A0required: > =C2=A0=C2=A0 - compatible > =C2=A0=C2=A0 - dmas > =C2=A0=C2=A0 - reg > =C2=A0=C2=A0 - clocks > =C2=A0 > +patternProperties: > +=C2=A0 "^.*@([0-9])$": > +=C2=A0=C2=A0=C2=A0 type: object > +=C2=A0=C2=A0=C2=A0 additionalProperties: true > +=C2=A0=C2=A0=C2=A0 properties: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 io-backends: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 description: | > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 AXI backend refer= ence > +=C2=A0=C2=A0=C2=A0 required: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - io-backends > + I wonder if it makes sense to have these specific bits only for the new com= patible? - Nuno S=C3=A1