From: Joshua Clayton <stillcompiling@gmail.com>
To: Alan Tull <atull@opensource.altera.com>,
Moritz Fischer <moritz.fischer@ettus.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>,
Fabio Estevam <fabio.estevam@nxp.com>,
Russell King <linux@armlinux.org.uk>,
Joshua Clayton <stillcompiling@gmail.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 4/5] ARM: dts: imx6q-evi: support cyclonespi
Date: Fri, 28 Oct 2016 09:56:41 -0700 [thread overview]
Message-ID: <36eb925f0c63c931bd406d1719e76e42b7d9432a.1477669745.git.stillcompiling@gmail.com> (raw)
In-Reply-To: <cover.1477669744.git.stillcompiling@gmail.com>
In-Reply-To: <cover.1477669744.git.stillcompiling@gmail.com>
Add support for Altera cyclone V FPGA connected to an spi port
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 6de21ff..bd0b85c 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -95,6 +95,15 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
status = "okay";
+
+ fpga_spi: cyclonespi@0 {
+ compatible = "altr,cyclone-ps-spi-fpga-mgr";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ pinctrl-0 = <&pinctrl_fpgaspi>;
+ config-gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+ status-gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+ };
};
&ecspi3 {
@@ -325,6 +334,13 @@
>;
};
+ pinctrl_fpgaspi: fpgaspigrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ >;
+ };
+
pinctrl_gpminand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
--
2.7.4
next prev parent reply other threads:[~2016-10-28 16:56 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-28 16:56 [PATCH v2 0/4] Altera Cyclone Passive Serial SPI FPGA Manager Joshua Clayton
2016-10-28 16:56 ` [PATCH v2 1/5] lib: add bitrev8x4() Joshua Clayton
[not found] ` <bc92eb1507448731163ae67fc888668d327f9168.1477669745.git.stillcompiling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-10-28 18:50 ` kbuild test robot
2016-10-28 16:56 ` [PATCH v2 2/5] doc: dt: add cyclone-spi binding document Joshua Clayton
[not found] ` <2de74f6d2f2689b8ef090a9017db2ffb3bd319cb.1477669745.git.stillcompiling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-10-31 6:16 ` Rob Herring
2016-10-28 16:56 ` [PATCH v2 3/5] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs Joshua Clayton
2016-10-28 18:55 ` kbuild test robot
2016-10-28 19:26 ` kbuild test robot
[not found] ` <202cdeff42a2de149c471630110a8b2657ccf5ca.1477669745.git.stillcompiling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-10-28 20:41 ` kbuild test robot
2016-10-28 21:05 ` Joshua Clayton
2016-10-28 16:56 ` Joshua Clayton [this message]
2016-10-28 16:56 ` [PATCH v2 5/5] fpga manager: cyclone-ps-spi: make delay variable Joshua Clayton
2016-10-28 17:41 ` Moritz Fischer
2016-10-28 19:49 ` Joshua Clayton
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