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Tue, 01 Sep 2026 05:33:54 -0700 (PDT) X-Received: by 2002:a17:90b:3c8f:b0:398:dc16:3c29 with SMTP id 98e67ed59e1d1-398dc16407dmr23760956a91.7.1788266033862; Tue, 01 Sep 2026 05:33:53 -0700 (PDT) Received: from [192.168.1.5] ([122.177.240.248]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3990d499811sm6791102a91.10.2026.09.01.05.33.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Sep 2026 05:33:53 -0700 (PDT) Message-ID: <36ebf737-e462-4c53-b6a9-51d26d4acc35@oss.qualcomm.com> Date: Tue, 1 Sep 2026 18:03:46 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord To: Shawn Guo , Vinod Koul Cc: Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Abel Vesa , Konrad Dybcio , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski References: <20260901095055.42229-1-shengchao.guo@oss.qualcomm.com> <20260901095055.42229-5-shengchao.guo@oss.qualcomm.com> Content-Language: en-US From: Krishna Kurapati In-Reply-To: <20260901095055.42229-5-shengchao.guo@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=OcyoyBTY c=1 sm=1 tr=0 ts=6a96c633 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=2sMs7eQfJahgYk7ien9XMw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=drxAI8maUB5UtpXgck8A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-ORIG-GUID: X4WdjB0ZiOP-LrnZU1ODMAwX3oexqfP2 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDExMSBTYWx0ZWRfX/GguaG9zqOUq QwC9gIh2A9D4xryuurwDRpxx8bAOcYzgSwMTrLuyv7R91n7c8ZRYlGCE4SK2r9wuREGhcTQqwOQ XsfVljTs9tdcBiRpiugvokxbkuwxYd0= X-Proofpoint-GUID: X4WdjB0ZiOP-LrnZU1ODMAwX3oexqfP2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDExMSBTYWx0ZWRfXzOEiDBcXcvng nhQ7IHwcO+JT+9pwJz3oLy3UXcceKaSjJAqcn9vcJWzdzKWeSamb6hjJIMhhDo4L1JWr7n5acnw k4ZjdWW+uZ1+bBoDAwTVmmxORDmt6LfZEtHBhHinQudwgnTmzDbu4jhMisfXPzV7aUq09wgSt+H 7gvqULpnN66VIpBe2RMaN3x3H7OL3r2bFFVWSmP3ckRFvCJNjEYoLcnmejQCkV0F1ytEiW4ttXd OKSvkAkiH5vM+VK58flxbSEtG+p46sk9Okyvw+NsBbcceJiGbfmK4sZZPGnCO64WYZpkCeG9Lv8 OQcHGV27+GNMgh1lq93BzEZD4buDZv3OOXFb009/3o9W3dFt6OFzIPWVsA5gBQHoSAglDxWXPMb ed/7f1a0FA8pC791Ay92ffsH3nIfPie7Vlz3pW56keSmZOTPR5RDUsXGsfs3xCZTy8HcdDff9va +NwJe5E8PKQSkTUfVlg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_03,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 malwarescore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010111 On 9/1/2026 3:20 PM, Shawn Guo wrote: > From: Bartosz Golaszewski > > Nord SoC provides two USB3+DP combo PHYs. Their initialisation sequences > are identical to sm8550, but the sub-blocks are not laid out the same way: > Nord adds a dedicated USB3_PCS_AON region at offset 0x1e00 and leaves > everything else where sm8550 has it. None of the existing offsets tables > describe that, so add a v6 table which is the v3 layout plus usb3_pcs_aon. > > Populating usb3_pcs_aon changes where the driver drives the I/O clamp when > entering and leaving autonomous mode: it now uses the real AON region > rather than falling back to PCS_MISC, which is what platforms with no AON > region do. > > The offsets were confirmed against the Nord register map for both PHY > instances, USB3_DP_PHY_0 at 0x088e1000 and USB3_DP_PHY_1 at 0x088e4000. > USB3_PCS_AON_CLAMP_ENABLE sits at offset 0x00 of the AON region with a > single CLAMP_EN_B bit, matching QPHY_V6_PCS_AON_CLAMP_ENABLE and CLAMP_EN. > > Signed-off-by: Bartosz Golaszewski > Assisted-by: LLM > Signed-off-by: Shawn Guo > --- > drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 66 +++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > index c39ced168d03..de82c7107c92 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > @@ -2690,6 +2690,23 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { > .dp_dp_phy = 0x2200, > }; > > +static const struct qmp_combo_offsets qmp_combo_offsets_v6 = { > + .com = 0x0000, > + .txa = 0x1200, > + .rxa = 0x1400, > + .txb = 0x1600, > + .rxb = 0x1800, > + .usb3_serdes = 0x1000, > + .usb3_pcs_misc = 0x1a00, > + .usb3_pcs = 0x1c00, > + .usb3_pcs_aon = 0x1e00, > + .usb3_pcs_usb = 0x1f00, > + .dp_serdes = 0x2000, > + .dp_txa = 0x2200, > + .dp_txb = 0x2600, > + .dp_dp_phy = 0x2a00, > +}; > + > static const struct qmp_combo_offsets qmp_combo_offsets_v8 = { > .com = 0x0000, > .txa = 0x1400, > @@ -3394,6 +3411,51 @@ static const struct qmp_phy_cfg glymur_usb3dpphy_cfg = { > .num_vregs = ARRAY_SIZE(qmp_phy_vreg_refgen), > }; > > +static const struct qmp_phy_cfg nord_usb3dpphy_cfg = { > + .offsets = &qmp_combo_offsets_v6, > + > + .serdes_tbl = sm8550_usb3_serdes_tbl, > + .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), > + .tx_tbl = sm8550_usb3_tx_tbl, > + .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), The values are different for the following registers: USB3_QSERDES_TXA_RCV_DETECT_LVL_2: SM8550=0x12, Nord=0x14 USB3_QSERDES_TXB_RCV_DETECT_LVL_2: SM8550=0x12, Nord=0x14 We need to add new tx_tbl for Nord. Regards, Krishna,