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Tue, 29 Oct 2024 05:17:09 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49T5H80D012175 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Oct 2024 05:17:08 GMT Received: from [10.216.61.9] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 22:17:03 -0700 Message-ID: <36ec01f4-c0fb-188e-06e9-10c7360a8ef0@quicinc.com> Date: Tue, 29 Oct 2024 10:47:00 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 1/1] RFC: dt bindings: Add property "brcm,gen3-eq-presets" Content-Language: en-US To: James Quinlan , Rob Herring CC: , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , , , Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley , "moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list References: <20241018182247.41130-1-james.quinlan@broadcom.com> <20241018182247.41130-2-james.quinlan@broadcom.com> <20241021190334.GA953710-robh@kernel.org> <77d3a1a9-c22d-0fd3-5942-91b9a3d74a43@quicinc.com> <954d6c11-ab4e-485f-8152-94bf38625f9c@broadcom.com> From: Krishna Chaitanya Chundru In-Reply-To: <954d6c11-ab4e-485f-8152-94bf38625f9c@broadcom.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: jcJScyLt2nHXQq_s-udtJhOC43-wGizG X-Proofpoint-GUID: jcJScyLt2nHXQq_s-udtJhOC43-wGizG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410290040 On 10/29/2024 12:21 AM, James Quinlan wrote: > On 10/24/24 21:08, Krishna Chaitanya Chundru wrote: >> >> >> On 10/22/2024 12:33 AM, Rob Herring wrote: >>> On Fri, Oct 18, 2024 at 02:22:45PM -0400, Jim Quinlan wrote: >>>> Support configuration of the GEN3 preset equalization settings, aka the >>>> Lane Equalization Control Register(s) of the Secondary PCI Express >>>> Extended Capability.  These registers are of type HwInit/RsvdP and >>>> typically set by FW.  In our case they are set by our RC host bridge >>>> driver using internal registers. >>>> >>>> Signed-off-by: Jim Quinlan >>>> --- >>>>   .../devicetree/bindings/pci/brcm,stb-pcie.yaml       | 12 >>>> ++++++++++++ >>>>   1 file changed, 12 insertions(+) >>>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml >>>> b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml >>>> index 0925c520195a..f965ad57f32f 100644 >>>> --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml >>>> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml >>>> @@ -104,6 +104,18 @@ properties: >>>>       minItems: 1 >>>>       maxItems: 3 >>>>   +  brcm,gen3-eq-presets: >>>> +    description: | >>>> +      A u16 array giving the GEN3 equilization presets, one for >>>> each lane. >>>> +      These values are destined for the 16bit registers known as the >>>> +      Lane Equalization Control Register(s) of the Secondary PCI >>>> Express >>>> +      Extended Capability.  In the array, lane 0 is first term, >>>> lane 1 next, >>>> +      etc. The contents of the entries reflect what is necessary for >>>> +      the current board and SoC, and the details of each preset are >>>> +      described in Section 7.27.4 of the PCI base spec, Revision 3.0. >>> >>> If these are defined by the PCIe spec, then why is it Broadcom specific >>> property? > Yes, I will remove the "brcm," prefix. >>> >> Hi Rob, >> >> qcom pcie driver also needs to program these presets as you suggested >> this can go to common pci bridge binding. >> >> from PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4.2 for data rates >> of  8.0 GT/s, 16.0 GT/s, and 32.0 GT/s uses one class of preset (P0 >> through P10) and where as data rates of 64.0 GT/s use different class of >> presets (Q0 through Q10) (Table 4-23). And data rates of 8.0 GT/s also >> have optional preset hints (Table 4-24). >> >> And there is possibility that for each data rate we may require >> different preset configuration. >> >> Can we have a dt binding for each data rate of 16 byte array. >> like gen3-eq-preset array, gen4-eq-preset array etc. > > Yes, that was the idea when using "genX-eq-preset", for X in {3,4...}. > > Keep in mind that this is an RFC; I have a backlog of commit submissions > before I can submit the code that uses this DT property.  If you > (Krishna) want to submit something now I'd be quite happy to go with > that.  I don't believe it is acceptable to submit a bindings commit w/o > code that uses it (if I'm incorrect I'll be glad to do a V2). > Hi Jim, I submitted a pull request for this. if you have any other suggestions or if we need to have any other details we can update this pull request. https://github.com/devicetree-org/dt-schema/pull/146 - Krishna Chaitanya. > Regards, > > Jim Quinlan > Broadcom STB/CM > >> >> - Krishna Chaitanya >>>> + >>>> +    $ref: /schemas/types.yaml#/definitions/uint16-array >>> >>> minItems: 1 >>> maxItems: 16 >>> >>> Last I saw, you can only have up to 16 lanes. >>> >>> Rob >>> >