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AJvYcCXjisa8em5AkYdRyaFHpO8vlw9k70HzgeXG9uGK21it7JS9t3RprFyJ3L8D/EAfOlYw+YibdpULfjK0@vger.kernel.org X-Gm-Message-State: AOJu0YzRdEkgaMptT1zJN+Pk6YnHuA5tXnWUGEPGV2qbfDzo7mPfi9rM 1gxT339G+SKDPlKKz8XSIg1PyC2YG0Cow1GtG7fdaExO9g5s0W74635Z17QKdNU= X-Google-Smtp-Source: AGHT+IGAa0EQAJZF+Lh7FUx2jhBZmgYnqQLqg9c45XbgMirrVdFpJCh5ZEZCWOekRRCzVbWbfunFNQ== X-Received: by 2002:adf:ef11:0:b0:37d:3dfc:949c with SMTP id ffacd0b85a97d-37d552957eemr1640400f8f.41.1728651970538; Fri, 11 Oct 2024 06:06:10 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b79fdc2sm3910675f8f.88.2024.10.11.06.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2024 06:06:10 -0700 (PDT) Date: Fri, 11 Oct 2024 16:06:06 +0300 From: Dan Carpenter To: Kevin Chen Cc: tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au, andrew@codeconstruct.com.au, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org Subject: Re: [PATCH v3 2/2] irqchip/aspeed-intc: Add support for AST27XX INTC Message-ID: <37525238-c9f8-4f0e-b4e5-4e2f05fab775@stanley.mountain> References: <20241009115813.2908803-1-kevin_chen@aspeedtech.com> <20241009115813.2908803-3-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241009115813.2908803-3-kevin_chen@aspeedtech.com> On Wed, Oct 09, 2024 at 07:58:13PM +0800, Kevin Chen wrote: > +static int __init aspeed_intc_ic_of_init(struct device_node *node, > + struct device_node *parent) > +{ > + struct aspeed_intc_ic *intc_ic; > + int ret = 0; > + int irq, i; > + > + intc_ic = kzalloc(sizeof(*intc_ic), GFP_KERNEL); > + if (!intc_ic) > + return -ENOMEM; > + > + intc_ic->base = of_iomap(node, 0); > + if (!intc_ic->base) { > + pr_err("Failed to iomap intc_ic base\n"); > + ret = -ENOMEM; > + goto err_free_ic; > + } > + writel(0xffffffff, intc_ic->base + INTC_INT_STATUS_REG); > + writel(0x0, intc_ic->base + INTC_INT_ENABLE_REG); > + > + intc_ic->irq_domain = irq_domain_add_linear(node, 32, > + &aspeed_intc_ic_irq_domain_ops, intc_ic); > + if (!intc_ic->irq_domain) { > + ret = -ENOMEM; > + goto err_iounmap; > + } > + > + raw_spin_lock_init(&intc_ic->gic_lock); > + raw_spin_lock_init(&intc_ic->intc_lock); > + > + /* Check all the irq numbers valid. If not, unmaps all the base and frees the data. */ > + for (i = 0; i < of_irq_count(node); i++) { > + irq = irq_of_parse_and_map(node, i); > + if (!irq) { > + pr_err("Failed to get irq number\n"); > + ret = -EINVAL; > + goto err_iounmap; > + } > + } > + > + for (i = 0; i < of_irq_count(node); i++) { > + irq = irq_of_parse_and_map(node, i); > + irq_set_chained_handler_and_data(irq, aspeed_intc_ic_irq_handler, intc_ic); There is an extra tab on this line. regards, dan carpenter > + } > + > + return 0;