* Re: [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node
2023-08-28 4:30 [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node Inochi Amaoto
@ 2023-08-28 6:33 ` Conor Dooley
2023-08-28 6:41 ` [PATCH] " Inochi Amaoto
2023-09-05 20:31 ` Jernej Škrabec
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Conor Dooley @ 2023-08-28 6:33 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Heiko Stuebner, Wei Fu, Pei Chen, Wenhan Chen, Guo Ren,
devicetree, linux-arm-kernel, linux-sunxi, linux-riscv,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3416 bytes --]
On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote:
> D1 has several pmu events supported by opensbi.
> These events can be used by perf for profiling.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
> ---
> changed from v3:
> 1. remove wrong event mapping of 0x0000a
> 2. add reference url of c906 events implementation (D1 only support events
> described in R1S0 user manual, but event mapping is the same)
Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
>
> changed from v2:
> 1. move pmu node from /soc to / to avoid warnings when checking.
>
> The meaning of T-HEAD events can be found in this pending patch:
> https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com
>
> The patch above also provides a example that shows how to setup
> environment and use perf with T-HEAD events.
> ---
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 8275630af977..53a984d78e3f 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 {
> #interrupt-cells = <2>;
> };
> };
> +
> + pmu {
> + compatible = "riscv,pmu";
> + riscv,event-to-mhpmcounters =
> + <0x00003 0x00003 0x00000008>,
> + <0x00004 0x00004 0x00000010>,
> + <0x00005 0x00005 0x00000200>,
> + <0x00006 0x00006 0x00000100>,
> + <0x10000 0x10000 0x00004000>,
> + <0x10001 0x10001 0x00008000>,
> + <0x10002 0x10002 0x00010000>,
> + <0x10003 0x10003 0x00020000>,
> + <0x10019 0x10019 0x00000040>,
> + <0x10021 0x10021 0x00000020>;
> + riscv,event-to-mhpmevent =
> + <0x00003 0x00000000 0x00000001>,
> + <0x00004 0x00000000 0x00000002>,
> + <0x00005 0x00000000 0x00000007>,
> + <0x00006 0x00000000 0x00000006>,
> + <0x10000 0x00000000 0x0000000c>,
> + <0x10001 0x00000000 0x0000000d>,
> + <0x10002 0x00000000 0x0000000e>,
> + <0x10003 0x00000000 0x0000000f>,
> + <0x10019 0x00000000 0x00000004>,
> + <0x10021 0x00000000 0x00000003>;
> + riscv,raw-event-to-mhpmcounters =
> + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
> + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
> + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
> + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
> + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
> + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
> + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
> + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
> + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
> + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
> + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
> + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
> + };
> };
> --
> 2.42.0
>
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] riscv: dts: allwinner: d1: Add PMU event node
2023-08-28 6:33 ` Conor Dooley
@ 2023-08-28 6:41 ` Inochi Amaoto
2023-08-28 6:50 ` Krzysztof Kozlowski
0 siblings, 1 reply; 8+ messages in thread
From: Inochi Amaoto @ 2023-08-28 6:41 UTC (permalink / raw)
To: Conor Dooley
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Inochi Amaoto, Heiko Stuebner, Wei Fu, Pei Chen,
Wenhan Chen, Guo Ren, devicetree, linux-arm-kernel, linux-sunxi,
linux-riscv, linux-kernel
>On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote:
>> D1 has several pmu events supported by opensbi.
>> These events can be used by perf for profiling.
>>
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
>> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
>> ---
>> changed from v3:
>> 1. remove wrong event mapping of 0x0000a
>> 2. add reference url of c906 events implementation (D1 only support events
>> described in R1S0 user manual, but event mapping is the same)
>
>Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT.
>Acked-by: Conor Dooley <conor.dooley@microchip.com>
>
>Thanks,
>Conor.
Sorry for this, I am not sure whether to preserve the ack.
Thank you for your ack again, and I will reserve this if no big change
happens.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] riscv: dts: allwinner: d1: Add PMU event node
2023-08-28 6:41 ` [PATCH] " Inochi Amaoto
@ 2023-08-28 6:50 ` Krzysztof Kozlowski
2023-08-28 6:59 ` [PATCH v4] " Inochi Amaoto
0 siblings, 1 reply; 8+ messages in thread
From: Krzysztof Kozlowski @ 2023-08-28 6:50 UTC (permalink / raw)
To: Inochi Amaoto, Conor Dooley
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Heiko Stuebner, Wei Fu, Pei Chen, Wenhan Chen, Guo Ren,
devicetree, linux-arm-kernel, linux-sunxi, linux-riscv,
linux-kernel
On 28/08/2023 08:41, Inochi Amaoto wrote:
>> On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote:
>>> D1 has several pmu events supported by opensbi.
>>> These events can be used by perf for profiling.
>>>
>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>>> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
>>> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
>>> ---
>>> changed from v3:
>>> 1. remove wrong event mapping of 0x0000a
>>> 2. add reference url of c906 events implementation (D1 only support events
>>> described in R1S0 user manual, but event mapping is the same)
>>
>> Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT.
>> Acked-by: Conor Dooley <conor.dooley@microchip.com>
>>
>> Thanks,
>> Conor.
>
> Sorry for this, I am not sure whether to preserve the ack.
> Thank you for your ack again, and I will reserve this if no big change
> happens.
https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node
2023-08-28 6:50 ` Krzysztof Kozlowski
@ 2023-08-28 6:59 ` Inochi Amaoto
0 siblings, 0 replies; 8+ messages in thread
From: Inochi Amaoto @ 2023-08-28 6:59 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Inochi Amaoto, Heiko Stuebner, Wei Fu, Pei Chen, Wenhan Chen,
Guo Ren, devicetree, linux-arm-kernel, linux-sunxi, linux-riscv,
linux-kernel
>On 28/08/2023 08:41, Inochi Amaoto wrote:
>>> On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote:
>>>> D1 has several pmu events supported by opensbi.
>>>> These events can be used by perf for profiling.
>>>>
>>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>>>> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
>>>> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
>>>> ---
>>>> changed from v3:
>>>> 1. remove wrong event mapping of 0x0000a
>>>> 2. add reference url of c906 events implementation (D1 only support events
>>>> described in R1S0 user manual, but event mapping is the same)
>>>
>>> Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT.
>>> Acked-by: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> Thanks,
>>> Conor.
>>
>> Sorry for this, I am not sure whether to preserve the ack.
>> Thank you for your ack again, and I will reserve this if no big change
>> happens.
>
>https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
>
>Best regards,
>Krzysztof
>
Thanks. I will take care of this.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node
2023-08-28 4:30 [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node Inochi Amaoto
2023-08-28 6:33 ` Conor Dooley
@ 2023-09-05 20:31 ` Jernej Škrabec
2023-09-06 0:50 ` Guo Ren
2023-09-24 20:09 ` Jernej Škrabec
3 siblings, 0 replies; 8+ messages in thread
From: Jernej Škrabec @ 2023-09-05 20:31 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Samuel Holland, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Inochi Amaoto, Heiko Stuebner, Wei Fu, Pei Chen, Wenhan Chen,
Guo Ren, Inochi Amaoto
Cc: devicetree, linux-arm-kernel, linux-sunxi, linux-riscv,
linux-kernel
On Monday, August 28, 2023 6:30:22 AM CEST Inochi Amaoto wrote:
> D1 has several pmu events supported by opensbi.
> These events can be used by perf for profiling.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
> Link:
> https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/
> pmu/rtl/aq_hpcp_top.v#L657
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
What's the status of dependencies? Are they merged?
Best regards,
Jernej
> ---
> changed from v3:
> 1. remove wrong event mapping of 0x0000a
> 2. add reference url of c906 events implementation (D1 only support events
> described in R1S0 user manual, but event mapping is the same)
>
> changed from v2:
> 1. move pmu node from /soc to / to avoid warnings when checking.
>
> The meaning of T-HEAD events can be found in this pending patch:
> https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BB
> E2A@IA1PR20MB4953.namprd20.prod.outlook.com
>
> The patch above also provides a example that shows how to setup
> environment and use perf with T-HEAD events.
> ---
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index
> 8275630af977..53a984d78e3f 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 {
> #interrupt-cells = <2>;
> };
> };
> +
> + pmu {
> + compatible = "riscv,pmu";
> + riscv,event-to-mhpmcounters =
> + <0x00003 0x00003 0x00000008>,
> + <0x00004 0x00004 0x00000010>,
> + <0x00005 0x00005 0x00000200>,
> + <0x00006 0x00006 0x00000100>,
> + <0x10000 0x10000 0x00004000>,
> + <0x10001 0x10001 0x00008000>,
> + <0x10002 0x10002 0x00010000>,
> + <0x10003 0x10003 0x00020000>,
> + <0x10019 0x10019 0x00000040>,
> + <0x10021 0x10021 0x00000020>;
> + riscv,event-to-mhpmevent =
> + <0x00003 0x00000000 0x00000001>,
> + <0x00004 0x00000000 0x00000002>,
> + <0x00005 0x00000000 0x00000007>,
> + <0x00006 0x00000000 0x00000006>,
> + <0x10000 0x00000000 0x0000000c>,
> + <0x10001 0x00000000 0x0000000d>,
> + <0x10002 0x00000000 0x0000000e>,
> + <0x10003 0x00000000 0x0000000f>,
> + <0x10019 0x00000000 0x00000004>,
> + <0x10021 0x00000000 0x00000003>;
> + riscv,raw-event-to-mhpmcounters =
> + <0x00000000 0x00000001 0xffffffff 0xffffffff
0x00000008>,
> + <0x00000000 0x00000002 0xffffffff 0xffffffff
0x00000010>,
> + <0x00000000 0x00000003 0xffffffff 0xffffffff
0x00000020>,
> + <0x00000000 0x00000004 0xffffffff 0xffffffff
0x00000040>,
> + <0x00000000 0x00000005 0xffffffff 0xffffffff
0x00000080>,
> + <0x00000000 0x00000006 0xffffffff 0xffffffff
0x00000100>,
> + <0x00000000 0x00000007 0xffffffff 0xffffffff
0x00000200>,
> + <0x00000000 0x0000000b 0xffffffff 0xffffffff
0x00002000>,
> + <0x00000000 0x0000000c 0xffffffff 0xffffffff
0x00004000>,
> + <0x00000000 0x0000000d 0xffffffff 0xffffffff
0x00008000>,
> + <0x00000000 0x0000000e 0xffffffff 0xffffffff
0x00010000>,
> + <0x00000000 0x0000000f 0xffffffff 0xffffffff
0x00020000>;
> + };
> };
> --
> 2.42.0
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node
2023-08-28 4:30 [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node Inochi Amaoto
2023-08-28 6:33 ` Conor Dooley
2023-09-05 20:31 ` Jernej Škrabec
@ 2023-09-06 0:50 ` Guo Ren
2023-09-24 20:09 ` Jernej Škrabec
3 siblings, 0 replies; 8+ messages in thread
From: Guo Ren @ 2023-09-06 0:50 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Heiko Stuebner, Wei Fu, Pei Chen, Wenhan Chen,
devicetree, linux-arm-kernel, linux-sunxi, linux-riscv,
linux-kernel
On Mon, Aug 28, 2023 at 12:29 PM Inochi Amaoto <inochiama@outlook.com> wrote:
>
> D1 has several pmu events supported by opensbi.
> These events can be used by perf for profiling.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
> ---
> changed from v3:
> 1. remove wrong event mapping of 0x0000a
> 2. add reference url of c906 events implementation (D1 only support events
> described in R1S0 user manual, but event mapping is the same)
>
> changed from v2:
> 1. move pmu node from /soc to / to avoid warnings when checking.
>
> The meaning of T-HEAD events can be found in this pending patch:
> https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com
>
> The patch above also provides a example that shows how to setup
> environment and use perf with T-HEAD events.
> ---
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 8275630af977..53a984d78e3f 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 {
> #interrupt-cells = <2>;
> };
> };
> +
> + pmu {
> + compatible = "riscv,pmu";
> + riscv,event-to-mhpmcounters =
> + <0x00003 0x00003 0x00000008>,
> + <0x00004 0x00004 0x00000010>,
> + <0x00005 0x00005 0x00000200>,
> + <0x00006 0x00006 0x00000100>,
> + <0x10000 0x10000 0x00004000>,
> + <0x10001 0x10001 0x00008000>,
> + <0x10002 0x10002 0x00010000>,
> + <0x10003 0x10003 0x00020000>,
> + <0x10019 0x10019 0x00000040>,
> + <0x10021 0x10021 0x00000020>;
> + riscv,event-to-mhpmevent =
> + <0x00003 0x00000000 0x00000001>,
> + <0x00004 0x00000000 0x00000002>,
> + <0x00005 0x00000000 0x00000007>,
> + <0x00006 0x00000000 0x00000006>,
> + <0x10000 0x00000000 0x0000000c>,
> + <0x10001 0x00000000 0x0000000d>,
> + <0x10002 0x00000000 0x0000000e>,
> + <0x10003 0x00000000 0x0000000f>,
> + <0x10019 0x00000000 0x00000004>,
> + <0x10021 0x00000000 0x00000003>;
> + riscv,raw-event-to-mhpmcounters =
> + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
> + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
> + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
> + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
> + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
> + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
> + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
> + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
> + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
> + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
> + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
> + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
> + };
> };
> --
> 2.42.0
>
Reviewed-by: Guo Ren <guoren@kernel.org>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node
2023-08-28 4:30 [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node Inochi Amaoto
` (2 preceding siblings ...)
2023-09-06 0:50 ` Guo Ren
@ 2023-09-24 20:09 ` Jernej Škrabec
3 siblings, 0 replies; 8+ messages in thread
From: Jernej Škrabec @ 2023-09-24 20:09 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Samuel Holland, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Inochi Amaoto, Heiko Stuebner, Wei Fu, Pei Chen, Wenhan Chen,
Guo Ren, Inochi Amaoto
Cc: devicetree, linux-arm-kernel, linux-sunxi, linux-riscv,
linux-kernel
Dne ponedeljek, 28. avgust 2023 ob 06:30:22 CEST je Inochi Amaoto napisal(a):
> D1 has several pmu events supported by opensbi.
> These events can be used by perf for profiling.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
Applied, thanks!
Best regards,
Jernej
> ---
> changed from v3:
> 1. remove wrong event mapping of 0x0000a
> 2. add reference url of c906 events implementation (D1 only support events
> described in R1S0 user manual, but event mapping is the same)
>
> changed from v2:
> 1. move pmu node from /soc to / to avoid warnings when checking.
>
> The meaning of T-HEAD events can be found in this pending patch:
> https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com
>
> The patch above also provides a example that shows how to setup
> environment and use perf with T-HEAD events.
> ---
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 8275630af977..53a984d78e3f 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 {
> #interrupt-cells = <2>;
> };
> };
> +
> + pmu {
> + compatible = "riscv,pmu";
> + riscv,event-to-mhpmcounters =
> + <0x00003 0x00003 0x00000008>,
> + <0x00004 0x00004 0x00000010>,
> + <0x00005 0x00005 0x00000200>,
> + <0x00006 0x00006 0x00000100>,
> + <0x10000 0x10000 0x00004000>,
> + <0x10001 0x10001 0x00008000>,
> + <0x10002 0x10002 0x00010000>,
> + <0x10003 0x10003 0x00020000>,
> + <0x10019 0x10019 0x00000040>,
> + <0x10021 0x10021 0x00000020>;
> + riscv,event-to-mhpmevent =
> + <0x00003 0x00000000 0x00000001>,
> + <0x00004 0x00000000 0x00000002>,
> + <0x00005 0x00000000 0x00000007>,
> + <0x00006 0x00000000 0x00000006>,
> + <0x10000 0x00000000 0x0000000c>,
> + <0x10001 0x00000000 0x0000000d>,
> + <0x10002 0x00000000 0x0000000e>,
> + <0x10003 0x00000000 0x0000000f>,
> + <0x10019 0x00000000 0x00000004>,
> + <0x10021 0x00000000 0x00000003>;
> + riscv,raw-event-to-mhpmcounters =
> + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
> + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
> + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
> + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
> + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
> + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
> + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
> + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
> + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
> + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
> + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
> + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
> + };
> };
> --
> 2.42.0
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread