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[83.9.31.20]) by smtp.gmail.com with ESMTPSA id f15-20020a50d54f000000b004aac3fd90fbsm222495edj.17.2023.02.06.03.01.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Feb 2023 03:01:08 -0800 (PST) Message-ID: <376236b5-9a5d-1c0b-65e4-346cc79e9de6@linaro.org> Date: Mon, 6 Feb 2023 12:01:04 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH 5/5] arm64: dst: qcom: sm8450: add dp controller Content-Language: en-US To: Neil Armstrong , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Kuogee Hsieh , Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230206-topic-sm8450-upstream-dp-controller-v1-0-f1345872ed19@linaro.org> <20230206-topic-sm8450-upstream-dp-controller-v1-5-f1345872ed19@linaro.org> From: Konrad Dybcio In-Reply-To: <20230206-topic-sm8450-upstream-dp-controller-v1-5-f1345872ed19@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 6.02.2023 11:17, Neil Armstrong wrote: > Add the Display Port controller subnode to the MDSS node. > > Signed-off-by: Neil Armstrong > --- > arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 +- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 82 +++++++++++++++++++++++++++++++-- > 2 files changed, 82 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts > index 5bdc2c1159ae..1b4ef79f74b3 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts > +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts > @@ -480,7 +480,9 @@ &mdss_dsi0_phy { > status = "okay"; > }; > > -&mdss_mdp { > +&mdss_dp0 { > + data-lanes = <0 1 2 3>; > + > status = "okay"; > }; This belongs in a separate patch. > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 757b7c56d5f5..8d83545d5e4a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -2745,13 +2745,20 @@ ports { > > port@0 { > reg = <0>; > - dpu_intf1_out: endpoint { > - remote-endpoint = <&mdss_dsi0_in>; > + dpu_intf0_out: endpoint { > + remote-endpoint = <&mdss_dp0_in>; > }; > }; > > port@1 { > reg = <1>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&mdss_dsi0_in>; > + }; > + }; > + > + port@2 { > + reg = <2>; > dpu_intf2_out: endpoint { > remote-endpoint = <&mdss_dsi1_in>; > }; > @@ -2789,6 +2796,75 @@ opp-500000000 { > }; > }; > > + mdss_dp0: displayport-controller@ae90000 { > + compatible = "qcom,sm8350-dp"; > + reg = <0 0xae90000 0 0x0fc>, Trim the leading zeroes from the size part, please. > + <0 0xae90200 0 0x0c0>, > + <0 0xae90400 0 0x770>, > + <0 0xae91000 0 0x098>; > + interrupt-parent = <&mdss>; > + interrupts = <12>; > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > + clock-names = "core_iface", "core_aux", > + "ctrl_link", > + "ctrl_link_iface", "stream_pixel"; Make this a vertical list, please. Konrad > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&usb_1_qmpphy 1>, > + <&usb_1_qmpphy 2>; > + > + phys = <&usb_1_qmpphy 1>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + operating-points-v2 = <&dp_opp_table>; > + power-domains = <&rpmhpd SM8450_MMCX>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dp0_in: endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + }; > + > + dp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > mdss_dsi0: dsi@ae94000 { > compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > reg = <0 0x0ae94000 0 0x400>; > @@ -2966,8 +3042,8 @@ dispcc: clock-controller@af00000 { > <&mdss_dsi0_phy 1>, > <&mdss_dsi1_phy 0>, > <&mdss_dsi1_phy 1>, > - <&usb_1_qmpphy 0>, > <&usb_1_qmpphy 1>, > + <&usb_1_qmpphy 2>, > <0>, /* dp1 */ > <0>, > <0>, /* dp2 */ >