From: Mikko Perttunen <mperttunen@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Thierry Reding <treding@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Sowjanya Komatineni <skomatineni@nvidia.com>,
Luca Ceresoli <luca.ceresoli@bootlin.com>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Svyatoslav Ryhel <clamor95@gmail.com>,
Dmitry Osipenko <digetx@gmail.com>,
Charan Pedumuru <charan.pedumuru@gmail.com>,
Svyatoslav Ryhel <clamor95@gmail.com>
Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-staging@lists.linux.dev
Subject: Re: [PATCH v1 15/19] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16
Date: Tue, 02 Sep 2025 10:09:47 +0900 [thread overview]
Message-ID: <3765586.e9J7NaK4W3@senjougahara> (raw)
In-Reply-To: <20250819121631.84280-16-clamor95@gmail.com>
On Tuesday, August 19, 2025 9:16 PM Svyatoslav Ryhel wrote:
> Add support for Bayer formats (RAW8 and RAW10) and YUV422_8 1X16 versions
> of existing YUV422_8 2X8.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> drivers/staging/media/tegra-video/tegra20.c | 71 ++++++++++++++++++++-
> 1 file changed, 69 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/staging/media/tegra-video/tegra20.c
> b/drivers/staging/media/tegra-video/tegra20.c index
> 67631e0c9ffc..b466fe7f4504 100644
> --- a/drivers/staging/media/tegra-video/tegra20.c
> +++ b/drivers/staging/media/tegra-video/tegra20.c
> @@ -186,6 +186,18 @@ static void tegra20_vi_get_input_formats(struct
> tegra_vi_channel *chan, case MEDIA_BUS_FMT_YVYU8_2X8:
> (*yuv_input_format) = VI_INPUT_YUV_INPUT_FORMAT_YVYU;
> break;
> + /* RAW8 */
> + case MEDIA_BUS_FMT_SBGGR8_1X8:
> + case MEDIA_BUS_FMT_SGBRG8_1X8:
> + case MEDIA_BUS_FMT_SGRBG8_1X8:
> + case MEDIA_BUS_FMT_SRGGB8_1X8:
> + /* RAW10 */
> + case MEDIA_BUS_FMT_SBGGR10_1X10:
> + case MEDIA_BUS_FMT_SGBRG10_1X10:
> + case MEDIA_BUS_FMT_SGRBG10_1X10:
> + case MEDIA_BUS_FMT_SRGGB10_1X10:
> + (*yuv_input_format) = VI_INPUT_INPUT_FORMAT_BAYER;
Should this be main_input_format instead of yuv_input_format?
> + break;
> }
> }
>
> @@ -220,6 +232,18 @@ static void tegra20_vi_get_output_formats(struct
> tegra_vi_channel *chan, case V4L2_PIX_FMT_YVU420:
> (*main_output_format) =
VI_OUTPUT_OUTPUT_FORMAT_YUV420PLANAR;
> break;
> + /* RAW8 */
> + case V4L2_PIX_FMT_SBGGR8:
> + case V4L2_PIX_FMT_SGBRG8:
> + case V4L2_PIX_FMT_SGRBG8:
> + case V4L2_PIX_FMT_SRGGB8:
> + /* RAW10 */
> + case V4L2_PIX_FMT_SBGGR10:
> + case V4L2_PIX_FMT_SGBRG10:
> + case V4L2_PIX_FMT_SGRBG10:
> + case V4L2_PIX_FMT_SRGGB10:
> + (*main_output_format) =
VI_OUTPUT_OUTPUT_FORMAT_VIP_BAYER_DIRECT;
> + break;
> }
> }
>
> @@ -300,6 +324,16 @@ static void tegra20_channel_queue_setup(struct
> tegra_vi_channel *chan) case V4L2_PIX_FMT_VYUY:
> case V4L2_PIX_FMT_YUYV:
> case V4L2_PIX_FMT_YVYU:
> + /* RAW8 */
> + case V4L2_PIX_FMT_SRGGB8:
> + case V4L2_PIX_FMT_SGRBG8:
> + case V4L2_PIX_FMT_SGBRG8:
> + case V4L2_PIX_FMT_SBGGR8:
> + /* RAW10 */
> + case V4L2_PIX_FMT_SRGGB10:
> + case V4L2_PIX_FMT_SGRBG10:
> + case V4L2_PIX_FMT_SGBRG10:
> + case V4L2_PIX_FMT_SBGGR10:
> if (chan->vflip)
> chan->start_offset += stride * (height - 1);
> if (chan->hflip)
> @@ -365,6 +399,19 @@ static void tegra20_channel_vi_buffer_setup(struct
> tegra_vi_channel *chan, tegra20_vi_write(chan,
> TEGRA_VI_VB0_BASE_ADDRESS(OUT_1), base); tegra20_vi_write(chan,
> TEGRA_VI_VB0_START_ADDRESS(OUT_1), base + chan->start_offset); break;
> + /* RAW8 */
> + case V4L2_PIX_FMT_SRGGB8:
> + case V4L2_PIX_FMT_SGRBG8:
> + case V4L2_PIX_FMT_SGBRG8:
> + case V4L2_PIX_FMT_SBGGR8:
> + /* RAW10 */
> + case V4L2_PIX_FMT_SRGGB10:
> + case V4L2_PIX_FMT_SGRBG10:
> + case V4L2_PIX_FMT_SGBRG10:
> + case V4L2_PIX_FMT_SBGGR10:
> + tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS(OUT_2),
base);
> + tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS(OUT_2),
base +
> chan->start_offset); + break;
> }
> }
>
> @@ -446,12 +493,15 @@ static int tegra20_chan_capture_kthread_start(void
> *data) static void tegra20_camera_capture_setup(struct tegra_vi_channel
> *chan) {
> u32 output_fourcc = chan->format.pixelformat;
> + u32 data_type = chan->fmtinfo->img_dt;
> int width = chan->format.width;
> int height = chan->format.height;
> int stride_l = chan->format.bytesperline;
> int stride_c = (output_fourcc == V4L2_PIX_FMT_YUV420 ||
> output_fourcc == V4L2_PIX_FMT_YVU420) ? 1 : 0;
> - int output_channel = OUT_1;
> + int output_channel = (data_type == TEGRA_IMAGE_DT_RAW8 ||
> + data_type == TEGRA_IMAGE_DT_RAW10) ?
> + OUT_2 : OUT_1;
> int main_output_format;
> int yuv_output_format;
>
> @@ -580,6 +630,20 @@ static const struct tegra_video_format
> tegra20_video_formats[] = { TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 16,
> YVYU),
> TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YUV420),
> TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YVU420),
> + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 16, UYVY),
> + TEGRA20_VIDEO_FMT(YUV422_8, 16, VYUY8_1X16, 16, VYUY),
> + TEGRA20_VIDEO_FMT(YUV422_8, 16, YUYV8_1X16, 16, YUYV),
> + TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_1X16, 16, YVYU),
> + /* RAW 8 */
> + TEGRA20_VIDEO_FMT(RAW8, 8, SRGGB8_1X8, 16, SRGGB8),
> + TEGRA20_VIDEO_FMT(RAW8, 8, SGRBG8_1X8, 16, SGRBG8),
> + TEGRA20_VIDEO_FMT(RAW8, 8, SGBRG8_1X8, 16, SGBRG8),
> + TEGRA20_VIDEO_FMT(RAW8, 8, SBGGR8_1X8, 16, SBGGR8),
> + /* RAW 10 */
> + TEGRA20_VIDEO_FMT(RAW10, 10, SRGGB10_1X10, 16, SRGGB10),
> + TEGRA20_VIDEO_FMT(RAW10, 10, SGRBG10_1X10, 16, SGRBG10),
> + TEGRA20_VIDEO_FMT(RAW10, 10, SGBRG10_1X10, 16, SGBRG10),
> + TEGRA20_VIDEO_FMT(RAW10, 10, SBGGR10_1X10, 16, SBGGR10),
> };
>
> const struct tegra_vi_soc tegra20_vi_soc = {
> @@ -606,9 +670,12 @@ const struct tegra_vi_soc tegra20_vi_soc = {
> static int tegra20_vip_start_streaming(struct tegra_vip_channel *vip_chan)
> {
> struct tegra_vi_channel *vi_chan =
> v4l2_get_subdev_hostdata(&vip_chan->subdev); + u32 data_type =
> vi_chan->fmtinfo->img_dt;
> int width = vi_chan->format.width;
> int height = vi_chan->format.height;
> - int output_channel = OUT_1;
> + int output_channel = (data_type == TEGRA_IMAGE_DT_RAW8 ||
> + data_type == TEGRA_IMAGE_DT_RAW10) ?
> + OUT_2 : OUT_1;
>
> unsigned int main_input_format;
> unsigned int yuv_input_format;
next prev parent reply other threads:[~2025-09-02 1:10 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-19 12:16 [PATCH v1 00/19] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 01/19] clk: tegra: init CSUS clock " Svyatoslav Ryhel
2025-08-27 4:09 ` Mikko Perttunen
2025-08-27 4:32 ` Svyatoslav
2025-08-27 10:36 ` Mikko Perttunen
2025-08-27 10:45 ` Svyatoslav Ryhel
2025-08-28 8:13 ` Mikko Perttunen
2025-08-28 8:28 ` Svyatoslav Ryhel
2025-08-28 10:15 ` Mikko Perttunen
2025-08-28 10:23 ` Svyatoslav Ryhel
2025-08-29 0:29 ` Mikko Perttunen
2025-08-29 7:05 ` Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 02/19] dt-bindings: clock: tegra20: Add IDs for CSI PAD clocks Svyatoslav Ryhel
2025-08-22 13:59 ` Rob Herring
2025-08-27 4:19 ` Mikko Perttunen
2025-08-27 4:28 ` Svyatoslav
2025-08-27 10:27 ` Mikko Perttunen
2025-08-29 6:54 ` Krzysztof Kozlowski
2025-08-19 12:16 ` [PATCH v1 03/19] clk: tegra30: add CSI PAD clock gates Svyatoslav Ryhel
2025-08-27 4:26 ` Mikko Perttunen
2025-08-29 0:44 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 04/19] dt-bindings: display: tegra: document Tegra30 VIP Svyatoslav Ryhel
2025-08-19 20:27 ` Rob Herring
2025-08-20 5:36 ` Svyatoslav Ryhel
2025-08-29 6:42 ` Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 05/19] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2025-08-27 4:29 ` Mikko Perttunen
2025-08-27 4:47 ` Svyatoslav
2025-08-29 0:56 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 06/19] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 07/19] staging: media: tegra-video: csi: parametrize MIPI calibration device presence Svyatoslav Ryhel
2025-09-02 0:46 ` Mikko Perttunen
2025-09-02 5:05 ` Svyatoslav Ryhel
2025-09-02 6:35 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 08/19] staging: media: tegra-video: vi: adjust get_selection op check Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 09/19] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2025-09-05 15:59 ` Luca Ceresoli
2025-09-05 16:05 ` Svyatoslav Ryhel
2025-09-09 10:13 ` Luca Ceresoli
2025-08-19 12:16 ` [PATCH v1 10/19] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2025-09-02 0:51 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 11/19] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2025-09-02 1:00 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 12/19] staging: media: tegra-video: tegra20: simplify format align calculations Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 13/19] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2025-09-05 16:08 ` Luca Ceresoli
2025-09-05 16:11 ` Svyatoslav Ryhel
2025-09-09 6:45 ` Luca Ceresoli
2025-08-19 12:16 ` [PATCH v1 14/19] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 15/19] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 Svyatoslav Ryhel
2025-09-02 1:09 ` Mikko Perttunen [this message]
2025-09-02 5:11 ` Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 16/19] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2025-09-02 1:16 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 17/19] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Svyatoslav Ryhel
2025-08-19 20:30 ` Rob Herring
2025-08-20 5:39 ` Svyatoslav Ryhel
2025-08-22 14:06 ` Rob Herring
2025-08-19 12:16 ` [PATCH v1 18/19] ARM: tegra: add CSI binding for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 19/19] staging: media: tegra-video: add CSI support " Svyatoslav Ryhel
2025-09-02 2:38 ` Mikko Perttunen
2025-09-02 5:51 ` Svyatoslav Ryhel
2025-09-02 6:17 ` Mikko Perttunen
2025-09-02 6:21 ` Svyatoslav Ryhel
2025-09-02 7:11 ` Dan Carpenter
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