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Wed, 12 Feb 2025 19:49:47 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51CJnkbx008705 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Feb 2025 19:49:46 GMT Received: from [10.216.10.30] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 12 Feb 2025 11:49:42 -0800 Message-ID: <37954fc4-27cc-4e5f-a8ef-0e7f4ac0e041@quicinc.com> Date: Thu, 13 Feb 2025 01:19:38 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/3] i3c: master: Add Qualcomm I3C master controller driver To: Krzysztof Kozlowski , Rob Herring CC: , , , , , , , References: <20250205143109.2955321-1-quic_msavaliy@quicinc.com> <20250205143109.2955321-3-quic_msavaliy@quicinc.com> <1e3a103d-d468-40c6-b03c-723427d7bb41@kernel.org> <20250211214128.GB1215572-robh@kernel.org> <5ae2fc10-c5fe-4400-8f15-de1fb7ef7144@kernel.org> Content-Language: en-US From: Mukesh Kumar Savaliya In-Reply-To: <5ae2fc10-c5fe-4400-8f15-de1fb7ef7144@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: QeskENwyDzHbaTTBMiHtPPqyhSpBm00y X-Proofpoint-ORIG-GUID: QeskENwyDzHbaTTBMiHtPPqyhSpBm00y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-12_06,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 phishscore=0 adultscore=0 spamscore=0 mlxscore=0 bulkscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502120141 On 2/13/2025 1:09 AM, Krzysztof Kozlowski wrote: > On 12/02/2025 20:29, Mukesh Kumar Savaliya wrote: >> Thanks a lot Rob ! sorry, i was late to respond on this while waiting >> for other comments agreements. >> >> On 2/12/2025 3:11 AM, Rob Herring wrote: >>> On Mon, Feb 10, 2025 at 09:41:28PM +0530, Mukesh Kumar Savaliya wrote: >>>> Thanks Krzysztof ! >>>> >>>> On 2/9/2025 5:10 PM, Krzysztof Kozlowski wrote: >>>>> On 07/02/2025 13:03, Mukesh Kumar Savaliya wrote: >>>>>>>> + gi3c->se.clk = devm_clk_get(&pdev->dev, "se-clk"); >>>>>>>> + if (IS_ERR(gi3c->se.clk)) { >>>>>>>> + ret = PTR_ERR(gi3c->se.clk); >>>>>>>> + dev_err(&pdev->dev, "Error getting SE Core clk %d\n", ret); >>>>>>>> + return ret; >>>>>>>> + } >>>>>>>> + >>>>>>>> + ret = device_property_read_u32(&pdev->dev, "se-clock-frequency", &gi3c->clk_src_freq); >>>>>>> >>>>>>> You never tested your DTS or this code... Drop >>>>>>> >>>>>> I have tested on SM8550 MTP only. Below entry in my internal/local DTSI. >>>>> >>>>> >>>>> And how is it supposed to work? Are you going to send us your local >>>>> internal DTSI? Is it going to pass any checks? >>>> was saying about code was testing with MTP. DTS was tested using dt-bindings >>>> check. >>> >>> make dtbs_check is how you test. >> Sure, we are running "make dt_binding_check >> DT_SCHEMA_FILES=qcom,i3c-master.yaml" > > Hm? Please read it again. You anyway have it documented in your company > guidebook, so I expect you follow that one *very* carefully because > reviewers repeating the same as your company book and then repeating > themselves three times is just too much. > sorry, i will run what Rob has pointed "make dtbs_check" as it's giving me exact clarity what to do. I just mentioned what i was doing. And as you pointed, will follow complete internal guide too if it's missing dtbs check. Thanks ! > Best regards, > Krzysztof