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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-591def1b2f6sm3462711e87.84.2025.10.21.02.48.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Oct 2025 02:48:55 -0700 (PDT) Message-ID: <3854e3a0-744c-4317-a6ed-e28edbabc4a3@linaro.org> Date: Tue, 21 Oct 2025 12:48:54 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc To: Luca Weiss , Taniya Das Cc: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Michael Turquette , Stephen Boyd , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Dmitry Baryshkov References: <20250303225521.1780611-1-vladimir.zapolskiy@linaro.org> <20250303225521.1780611-3-vladimir.zapolskiy@linaro.org> <3210a484-b9c3-4399-bee1-9f5bbc90034c@linaro.org> From: Vladimir Zapolskiy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Luca. On 10/17/25 17:05, Luca Weiss wrote: > Hi Taniya, > > On Thu Mar 13, 2025 at 12:57 PM CET, Taniya Das wrote: >> >> >> On 3/13/2025 1:22 PM, Luca Weiss wrote: >>> Hi Taniya, >>> >>> On Thu Mar 13, 2025 at 5:39 AM CET, Taniya Das wrote: >>>> >>>> >>>> On 3/4/2025 2:10 PM, Dmitry Baryshkov wrote: >>>>> On Tue, 4 Mar 2025 at 09:37, Vladimir Zapolskiy >>>>> wrote: >>>>>> >>>>>> On 3/4/25 01:53, Dmitry Baryshkov wrote: >>>>>>> On Tue, Mar 04, 2025 at 12:55:21AM +0200, Vladimir Zapolskiy wrote: >>>>>>>> SM8550 Camera Clock Controller shall enable both MXC and MMCX power >>>>>>>> domains. >>>>>>> >>>>>>> Are those really required to access the registers of the cammcc? Or is >>>>>>> one of those (MXC?) required to setup PLLs? Also, is this applicable >>>>>>> only to sm8550 or to other similar clock controllers? >>>>>> >>>>>> Due to the described problem I experience a fatal CPU stall on SM8550-QRD, >>>>>> not on any SM8450 or SM8650 powered board for instance, however it does >>>>>> not exclude an option that the problem has to be fixed for other clock >>>>>> controllers, but it's Qualcomm to confirm any other touched platforms, >>>>> >>>>> Please work with Taniya to identify used power domains. >>>>> >>>> >>>> CAMCC requires both MMCX and MXC to be functional. >>> >>> Could you check whether any clock controllers on SM6350/SM7225 (Bitra) >>> need multiple power domains, or in general which clock controller uses >>> which power domain. >>> >>> That SoC has camcc, dispcc, gcc, gpucc, npucc and videocc. >>> >>> That'd be highly appreciated since I've been hitting weird issues there >>> that could be explained by some missing power domains. >>> >> >> Hi Luca, >> >> The targets you mentioned does not have any have multiple rail >> dependency, but could you share the weird issues with respect to clock >> controller I can take a look. > > Coming back to this, I've taken a shot at camera on SM6350 (Fairphone 4) > again, but again hitting some clock issues. > > For reference, I am testing with following change: > https://lore.kernel.org/linux-arm-msm/20250911011218.861322-3-vladimir.zapolskiy@linaro.org/ > > Trying to enable CAMCC_MCLK1_CLK - wired up to the IMX576 camera sensor > on this phone - results in following error. > > [ 3.140232] ------------[ cut here ]------------ > [ 3.141264] camcc_mclk1_clk status stuck at 'off' > [ 3.141276] WARNING: CPU: 6 PID: 12 at drivers/clk/qcom/clk-branch.c:87 clk_branch_toggle+0x170/0x190 > > Checking the driver against downstream driver, it looks like the RCGs > should be using clk_rcg2_shared_ops because of enable_safe_config in > downstream, but changing that doesn't really improve the situation, but > it does change the error message to this: > > [ 2.933254] ------------[ cut here ]------------ > [ 2.933961] camcc_mclk1_clk_src: rcg didn't update its configuration. > [ 2.933970] WARNING: CPU: 7 PID: 12 at drivers/clk/qcom/clk-rcg2.c:136 update_config+0xd4/0xe4 > > I've also noticed that some camcc drivers take in GCC_CAMERA_AHB_CLK as > iface clk, could something like this be missing on sm6350? > > I'd appreciate any help or tips for resolving this. > Recently one particular problem related to MCLK was identified by me on QRB5165/RB5, and it was reported to Bjorn over IRC, namely it's not possible to toggle MCLK clock enable/disable state, when TITAN GDSC power domain is set off. I'm working on fixing the issue (a change under clk/qcom), since it's of an importance for a customer as well. I can't be totally sure that it's right the same problem as the one reported by you above, but it looks very similar, as a fast workaround please consider to set an ALWAYS_ON flag of TITAN GDSC, and at least a report from you that this actually helps would be nice to get. -- Best wishes, Vladimir