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([2a02:810d:15c0:828:8fa0:9989:3f72:b14f]) by smtp.gmail.com with ESMTPSA id f17-20020a170906739100b0094e5679dd2csm532308ejl.165.2023.04.12.01.28.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Apr 2023 01:28:31 -0700 (PDT) Message-ID: <38575aee-139c-688c-21a0-69844e5ae1c2@linaro.org> Date: Wed, 12 Apr 2023 10:28:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v4 2/7] dt-bindings: phy: Add StarFive JH7110 PCIe document Content-Language: en-US To: Minda Chen , Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Mason Huo References: <20230406015216.27034-1-minda.chen@starfivetech.com> <20230406015216.27034-3-minda.chen@starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <20230406015216.27034-3-minda.chen@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 06/04/2023 03:52, Minda Chen wrote: > Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. > PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Subject: drop second/last, redundant "document". The "dt-bindings" prefix is already stating that this is documentation. > > Signed-off-by: Minda Chen > --- > .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml > new file mode 100644 > index 000000000000..1b868f75ddae > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive PCIe 2.0 PHY JH7110 Unless you plan to add here more compatibles, but then use enum for compatible, not const. > + > +maintainers: > + - Minda Chen > + > +properties: > + compatible: > + const: starfive,jh7110-pcie-phy > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 0 > + > + starfive,sys-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle to System Register Controller sys_syscon node. > + - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY. No improvements here. > + description: > + The phandle to System Register Controller syscon node and the PHY connect offset > + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller. > + > + starfive,stg-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle to System Register Controller stg_syscon node. > + - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register. > + - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register. No improvements. Best regards, Krzysztof