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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3a82198eesm209111166b.184.2025.03.19.07.12.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Mar 2025 07:12:53 -0700 (PDT) Message-ID: <38677d30-e2ac-427b-9de6-9e5f1465e7a3@oss.qualcomm.com> Date: Wed, 19 Mar 2025 15:12:50 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 02/10] arm64: dts: qcom: qcs6490-rb3gen2: Add TC956x PCIe switch node To: Dmitry Baryshkov , Krishna Chaitanya Chundru Cc: Krishna Chaitanya Chundru , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski , quic_vbadigan@quicnic.com, amitk@kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> <20250225-qps615_v4_1-v4-2-e08633a7bdf8@oss.qualcomm.com> <8a2bce29-95dc-53b0-0516-25a380d94532@oss.qualcomm.com> <16a9ff11-70dc-22e9-bd3c-ed10bf8b4fea@quicinc.com> <303194d4-d342-ea4c-0bb6-5f5d0297ba23@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=SKhCVPvH c=1 sm=1 tr=0 ts=67dad0e7 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=9XCCm2T1sdJvpMR4L6IA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: iqCIqIy9bRk3EQ_rOYRHeQhCf1gAb6vW X-Proofpoint-GUID: iqCIqIy9bRk3EQ_rOYRHeQhCf1gAb6vW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-19_05,2025-03-19_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 mlxscore=0 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503190096 On 3/19/25 12:06 PM, Dmitry Baryshkov wrote: > On Wed, Mar 19, 2025 at 04:16:33PM +0530, Krishna Chaitanya Chundru wrote: >> >> >> On 3/19/2025 3:51 PM, Dmitry Baryshkov wrote: >>> On Wed, Mar 19, 2025 at 03:46:00PM +0530, Krishna Chaitanya Chundru wrote: >>>> >>>> >>>> On 3/19/2025 3:43 PM, Dmitry Baryshkov wrote: >>>>> On Wed, Mar 19, 2025 at 09:14:22AM +0530, Krishna Chaitanya Chundru wrote: >>>>>> >>>>>> >>>>>> On 3/18/2025 10:30 PM, Dmitry Baryshkov wrote: >>>>>>> On Tue, 18 Mar 2025 at 18:11, Krishna Chaitanya Chundru >>>>>>> wrote: >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> On 3/17/2025 4:57 PM, Dmitry Baryshkov wrote: >>>>>>>>> On Tue, Feb 25, 2025 at 03:03:59PM +0530, Krishna Chaitanya Chundru wrote: >>>>>>>>>> Add a node for the TC956x PCIe switch, which has three downstream ports. >>>>>>>>>> Two embedded Ethernet devices are present on one of the downstream ports. >>>>>>>>>> >>>>>>>>>> Power to the TC956x is supplied through two LDO regulators, controlled by >>>>>>>>>> two GPIOs, which are added as fixed regulators. Configure the TC956x >>>>>>>>>> through I2C. >>>>>>>>>> >>>>>>>>>> Signed-off-by: Krishna Chaitanya Chundru >>>>>>>>>> Reviewed-by: Bjorn Andersson >>>>>>>>>> Acked-by: Manivannan Sadhasivam >>>>>>>>>> --- >>>>>>>>>> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 116 +++++++++++++++++++++++++++ >>>>>>>>>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- >>>>>>>>>> 2 files changed, 117 insertions(+), 1 deletion(-) >>>>>>>>>> >>>>>>>>>> @@ -735,6 +760,75 @@ &pcie1_phy { >>>>>>>>>> status = "okay"; >>>>>>>>>> }; >>>>>>>>>> >>>>>>>>>> +&pcie1_port { >>>>>>>>>> + pcie@0,0 { >>>>>>>>>> + compatible = "pci1179,0623", "pciclass,0604"; >>>>>>>>>> + reg = <0x10000 0x0 0x0 0x0 0x0>; >>>>>>>>>> + #address-cells = <3>; >>>>>>>>>> + #size-cells = <2>; >>>>>>>>>> + >>>>>>>>>> + device_type = "pci"; >>>>>>>>>> + ranges; >>>>>>>>>> + bus-range = <0x2 0xff>; >>>>>>>>>> + >>>>>>>>>> + vddc-supply = <&vdd_ntn_0p9>; >>>>>>>>>> + vdd18-supply = <&vdd_ntn_1p8>; >>>>>>>>>> + vdd09-supply = <&vdd_ntn_0p9>; >>>>>>>>>> + vddio1-supply = <&vdd_ntn_1p8>; >>>>>>>>>> + vddio2-supply = <&vdd_ntn_1p8>; >>>>>>>>>> + vddio18-supply = <&vdd_ntn_1p8>; >>>>>>>>>> + >>>>>>>>>> + i2c-parent = <&i2c0 0x77>; >>>>>>>>>> + >>>>>>>>>> + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; >>>>>>>>>> + >>>>>>>>> >>>>>>>>> I think I've responded here, but I'm not sure where the message went: >>>>>>>>> please add pinctrl entry for this pin. >>>>>>>>> >>>>>>>> Do we need to also add pinctrl property for this node and refer the >>>>>>>> pinctrl entry for this pin? >>>>>>> >>>>>>> I think that is what I've asked for, was that not? >>>>>> Currently there is no pincntrl property defined for this. >>>>> >>>>> Does it need to be defined separately / specially? >>>>> >>>> yes we need to define this property now. >>> >>> Could you please point out existing schema files defining those >>> properties? >> sorry I was not able to get which schema file you are requesting for, >> if it is tc956x it is in this series only. >> >> What I understood from these conversation is we need to define pinctrl >> property and refer the reset gpio pin in next series. If it was wrong >> please correct me. > > You claimed that pinctrl properties (there are several of those) are to > be defined in the schema for TC956x. I asked you to point out other > schema files which define those properties for the devices that use > GPIO pins. pinctrl-x is part of common schema (see gh/devicetree-org/dt-schema/) Konrad