From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A821F2F7EF7; Fri, 3 Jul 2026 06:26:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783060012; cv=none; b=ukzlammV3i6tvPu3oHvCDk9jYfJm1hiX/wFcrCqxfq2rG3SQRD7/Q8HC5rblKMs3enXcE6LqpV4wKd/9GNtpN8ulnBTDxH0eQtO+4+85TudR/Jh9lasExT/aWnshdJ8YNiuantesINkpf7jFCtgG3C9H2xefrLGSf2YiDMStYWU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783060012; c=relaxed/simple; bh=PwfMhtL+eOlDTa+uAjkuvpHphWEcJWsfI0fKLweKKyI=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=ju5qh5DxGpft6S+/Q89eA/eBVJLic0+L5s/krgt8cItuphWn9F1S0cg2QiM4LpOzpws7KZFSvoguJeeJ9k9HGhpGhypH3UF71aD42VfjBYCUy2xtSQW5gO6vRpuqOpXNDSepVwLiV1IBVeK2ra5ZXP9myMZMRK0frFzLzTm/dxk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VgN11bcR; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VgN11bcR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2C0841F000E9; Fri, 3 Jul 2026 06:26:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783060011; bh=SSDpIKdc9KFNJYo6OB/lyw6kWfRv+7YvtWzJeQyNp50=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=VgN11bcR5iNSut0IP3G/sxsx1nT/rw0o3PK+DUrmLm84w8osacOg+hsgMFOCztnFj 3/MYWUDOCYjBlnG0MRUIEibl+rUc/RBpK5Gj+i16uFtCbJ/F8nRPa93v35J0txqNT3 jAJX+bqXlvpdwGdOsF1vZCqPv+r/ZsHqLDxj9nHvfPhpJRNbwC749rCwYQFw6eBe0g 57kDWjD8FJRZ84lCWwQrL791mPc2dXyIT5+LIJeHDZUuc7rp94ny3KFAxF+7XVMtQE 9IEASN3l43CkLH4AiLjFqZKiigaaqu9kIKznbwoM2miaxU+ilODq+QCMnsZ6P0pkKq cuiCNgmzxs9qA== Message-ID: <387ff0d7-256e-4b18-b864-37a0ec3c9d9d@kernel.org> Date: Fri, 3 Jul 2026 08:26:43 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 01/12] dt-bindings: soc: zte: Add zx297520v3 top clock and reset bindings To: =?UTF-8?Q?Stefan_D=C3=B6singer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20260702-zx29clk-v6-0-377b704f80c4@gmail.com> <20260702-zx29clk-v6-1-377b704f80c4@gmail.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; keydata= xsFNBFVDQq4BEAC6KeLOfFsAvFMBsrCrJ2bCalhPv5+KQF2PS2+iwZI8BpRZoV+Bd5kWvN79 cFgcqTTuNHjAvxtUG8pQgGTHAObYs6xeYJtjUH0ZX6ndJ33FJYf5V3yXqqjcZ30FgHzJCFUu JMp7PSyMPzpUXfU12yfcRYVEMQrmplNZssmYhiTeVicuOOypWugZKVLGNm0IweVCaZ/DJDIH gNbpvVwjcKYrx85m9cBVEBUGaQP6AT7qlVCkrf50v8bofSIyVa2xmubbAwwFA1oxoOusjPIE J3iadrwpFvsZjF5uHAKS+7wHLoW9hVzOnLbX6ajk5Hf8Pb1m+VH/E8bPBNNYKkfTtypTDUCj NYcd27tjnXfG+SDs/EXNUAIRefCyvaRG7oRYF3Ec+2RgQDRnmmjCjoQNbFrJvJkFHlPeHaeS BosGY+XWKydnmsfY7SSnjAzLUGAFhLd/XDVpb1Een2XucPpKvt9ORF+48gy12FA5GduRLhQU vK4tU7ojoem/G23PcowM1CwPurC8sAVsQb9KmwTGh7rVz3ks3w/zfGBy3+WmLg++C2Wct6nM Pd8/6CBVjEWqD06/RjI2AnjIq5fSEH/BIfXXfC68nMp9BZoy3So4ZsbOlBmtAPvMYX6U8VwD TNeBxJu5Ex0Izf1NV9CzC3nNaFUYOY8KfN01X5SExAoVTr09ewARAQABzSVLcnp5c3p0b2Yg S296bG93c2tpIDxrcnprQGtlcm5lbC5vcmc+wsGPBBMBCgA5AhsDBgsJCAcDAgYVCAIJCgsE FgIDAQIeAQIXgBYhBJvQfg4MUfjVlne3VBuTQ307QWKbBQJp2mE8AAoJEBuTQ307QWKbeaIP /ihHTkTW4KsN/DQ945JJbyu5tI0J80Wue7QyyLPglyKfhgb5cLLNPpOC8cCIJsc7+W3i2P38 s2c1cOH6CYGE7E9ur3Vfme8NW2S2I/Z8VC7bZnzyS23wT17LrsdS/qCpx4o8U+pt/xdXDKph EGRYrIEmMpUWvyYzyYKGIe25FtaayIIKpq8eZYyFcp2f/sG5IkOW5uZzHPMPdcm87jU7fyuQ rAU2vx9r+ulUfQ/q9Z2roC/ode3l7t2pN7BCBCsUDp6JCrUyZrtT1e7EbA0ZRP3aOBNk2P2E DQOgJGjGdO5Yx2Y9LFtltu6JbsBJHi1syGRX3AtQYOMc4Y1WGoeZJmMlvKj2ZqqXNkcWi2DS IQEWB0uW6CqFsBBIMGDa+6OzdaVO/uAVXWDWml02Men3CILdI1MbVjoh8ECqYUY7OQ+JJvNN vnliuq5WM3Ghd3jg/LZZrxXjdIginRHFQCjIJYLKpLZWm1/iDFedcfzqRNYmTtqscdCNHW41 oT3Z7BmO9xwdjuwBS6nmS6JJwkbf5Ot2QR4pB/DRU7ZwjT1qHe+9r9gF32wXVQatHNGK/VVu sfwOnkdxCWkp/qb2gdQRmZh+SedStWshigH6sNfuHBloF/q+hjMRc8b2m326OZdrbSHwY1Sz vti8Hn7n8NjdHO9LKB7BIdjkA9DA5WsqOuVCzsFNBFVDXDQBEADNkrQYSREUL4D3Gws46JEo Z9HEQOKtkrwjrzlw/tCmqVzERRPvz2Xg8n7+HRCrgqnodIYoUh5WsU84N03KlLueMNsWLJBv BaubYN4JuJIdRr4dS4oyF1/fQAQPHh8Thpiz0SAZFx6iWKB7Qrz3OrGCjTPcW6eiOMheesVS 5hxietSmlin+SilmIAPZHx7n242u6kdHOh+/SyLImKn/dh9RzatVpUKbv34eP1wAGldWsRxb f3WP9pFNObSzI/Bo3kA89Xx2rO2roC+Gq4LeHvo7ptzcLcrqaHUAcZ3CgFG88CnA6z6lBZn0 WyewEcPOPdcUB2Q7D/NiUY+HDiV99rAYPJztjeTrBSTnHeSBPb+qn5ZZGQwIdUW9YegxWKvX XHTwB5eMzo/RB6vffwqcnHDoe0q7VgzRRZJwpi6aMIXLfeWZ5Wrwaw2zldFuO4Dt91pFzBSO IpeMtfgb/Pfe/a1WJ/GgaIRIBE+NUqckM+3zJHGmVPqJP/h2Iwv6nw8U+7Yyl6gUBLHFTg2h YnLFJI4Xjg+AX1hHFVKmvl3VBHIsBv0oDcsQWXqY+NaFahT0lRPjYtrTa1v3tem/JoFzZ4B0 p27K+qQCF2R96hVvuEyjzBmdq2esyE6zIqftdo4MOJho8uctOiWbwNNq2U9pPWmu4vXVFBYI GmpyNPYzRm0QPwARAQABwsF2BBgBCgAgAhsMFiEEm9B+DgxR+NWWd7dUG5NDfTtBYpsFAmna YUkACgkQG5NDfTtBYptX+BAApg32CkxwNucNEi8WfWA8oKkW0y8YDuY6ORMo9FWNGiT/OTy0 vyJrLocrpn86zwfjVp+eCrssPYh8eqJfnWqmYv6ACQtHPYzPZQ3mSo8H97Z01oUxITzCxpXm ZkLgPIqtDPcC2E3dPM/fVxcyowM8XsaMA9wcsaUYrta8toOq2b9tKcjleKMfMrm0gQ9u7wUc QbLkwj6TCLOwucb07GXzLTNF9PZmaDUpKAZjMjmrW+le+SFvQbhamx0rxLWPR0NWntXpbCn+ +ACch03p/JyTBVktxFsFyCt7pTPE1kEaeuXBTe/a2D9iQvRxRW19LvuO2e59/u1wYUiH/orz wbIC2S4dBsPAPihL3ztOU1yE86GPyQtSE0kU+/7snnLt4QGi6PChf3t5gnNjAzjUUovO8rgI c+5yN5heq5loYHgK6OQ9OlHzsPHO9e9MOQcKlFycs1pyijFGzDwdNUm/SchK8iWT2QApTx4A K9bCVaboTA2T77QYkRcRJYSsO1alGX0ome/hMLD1daXlkrNUp1HWa3K4iytLRXjCSIorWiGs n+q3krnpXu3TFkA8qtOFZMdnIiFuiq1yLT8hptsV5xh1TA2nsVvSYiaCr3q4s4BKjS/KrLDb qoxzw8ISjdUp4pA85vb6YLCmb39NgidD+7PmAr65lBNveIFynTgsja1rRQ4= In-Reply-To: <20260702-zx29clk-v6-1-377b704f80c4@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 02/07/2026 22:27, Stefan Dösinger wrote: > These SoCs have 3 clock and reset controllers: Top, Matrix and LSP. The > separation of concerns between Top and Matrix and the interface between > them is poorly defined in the hardware, so the bindings list all > potential PLL clocks that might be passed between them. > > Generally every device has two clocks (one work clock, and one that > connects it to the bus, I call it PCLK), two reset bits (I don't know > what the difference is - sometimes asserting one is enough to reset the > device, sometimes both need to be asserted). PCLK and WCLK are > controlled by individual gates. Some devices have a mux and/or a > divider for their work clock. Some devices, like the GPIO controller, > only have reset bits and no clocks. > > The top clock controller is fed by a 26mhz external oscillator and has 4 > PLLs to generate other clock rates. ZTE's kernel mostly relies on the > boot ROM to set up PLLs, but one LTE-Related PLL is not configured > on some boards. Therefore my driver contains code to program PLLs. It > produces identical settings as the boot ROM for the pre-programmed > frequencies. > > Not all clocks will have an explicit user in the end. I am defining a > lot of them simply to shut them off. The boot loader sets up a few of > the proprietary timers, which will send regular IRQs (although the > kernel of course doesn't need to listen to them). I don't plan to add a > driver for the proprietary timer as I see no use for them - the ARM arch > timer works just fine. I will add a driver for the very similar > proprietary watchdog though. > > The clock list in this patch is pretty complete but not exhaustive. > There are other bits that are enabled, but I couldn't deduce what they > are controlling by trial and error. Some of them seem to do nothing. > Others cause an instant hang of the board when disabled. It is quite > likely that a handful more clocks will be added in the future, but not a > large number. > > Signed-off-by: Stefan Dösinger > > --- > > Changes v5->v6: > Set value for syscon-reboot example (Sashiko). It was my intention to > set only the lowest bit, and I think Sashiko is right that without > 'value' being set, all other bits are actively set to 0. It shouldn't > matter given my understanding of the hardware (afaics all other bits are > ignored), but actively clearing bits was not my intention. > > I haven't changed the name match for "syscon-reboot". I see plenty of > examples of hardcoding this string as opposed to having a regex for > syscon-reboot@12345678 in other bindings. > > Changes v4->v5: > > Rename from zte,zx297520v3-topclk to zte,zx297520v3-topcrm and move to > soc/zte > Fix path in MAINTAINERS > Add syscon-reboot node to the binding > Give the USB and HSIC PHY resets their own reset control > --- > .../bindings/soc/zte/zte,zx297520v3-topcrm.yaml | 86 +++++++++++++++++++ > MAINTAINERS | 3 + > include/dt-bindings/clock/zte,zx297520v3-clk.h | 97 ++++++++++++++++++++++ > include/dt-bindings/reset/zte,zx297520v3-reset.h | 32 +++++++ > 4 files changed, 218 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-topcrm.yaml b/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-topcrm.yaml > new file mode 100644 > index 000000000000..5a5d97120056 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-topcrm.yaml > @@ -0,0 +1,86 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/zte/zte,zx297520v3-topcrm.yaml# Also, this cannot be placed in soc. Clock and reset controllers DO NOT go to the soc directory. Place in it clocks. A nit, subject: drop second/last, redundant "bindings". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23 Best regards, Krzysztof