Re: [PATCH 2/2] arm64: dts: qcom: Enable tsens and thermal for sa8775p SoC

[Priyansh Jain <quic_priyjain@quicinc.com>]

Hi Konrad,

On 8/21/2023 5:25 PM, Konrad Dybcio wrote:
> On 21.08.2023 13:29, Priyansh Jain wrote:
>> Add tsens and thermal devicetree node for sa8775p SoC.
>>
>> Signed-off-by: Priyansh Jain <quic_priyjain@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1096 +++++++++++++++++++++++++
>>   1 file changed, 1096 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index b130136acffe..b9c622b3bf7e 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -2306,6 +2306,1102 @@
>>   
>>   			#freq-domain-cells = <1>;
>>   		};
>> +
>> +		tsens0: thermal-sensor@c222000 {
>> +			compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
>> +			reg = <0x0C263000 0x1ff>,  /* TM */
>> +				<0x0C222000 0x1ff>; /* SROT */
> 1. Test your patches. This will obviously not work due to the
>     #address/size-cells values of /soc@0.
Yes this needs to be updated, Will update in the next revision.
> 
> 2. Use lowercase hex.
Sure will update in next revision.
> 3. Align subsequent entries for a property with the previous line
> 
Sure will update in next revision.
> 4. Are you sure SROT is 0x1ff-long?
> 
Yes it can be updated to 0x8 , will update in next revision.
> 5. The usefulness of these comments is questionable, many DTs have
>     them because of copypasta but I think it's time to stop that.
> 
Yes will remove them in next revision.
> 6. No pdc wake-capable interrupts?
Yes they don't need to be pdc wakeup capable.
> 
>> +			#qcom,sensors = <12>;
>> +			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
>> +				<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "uplow","critical";
> Missing space after the comma
Yes will update in next revision.
> 
> Please move interrupt properties right after 'reg'.
Sure will update in next revision.
> Konrad