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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0bd48fsm38623195ad.129.2024.10.22.02.14.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Oct 2024 02:14:36 -0700 (PDT) Message-ID: <38aba46a-c5e5-4832-8a73-4260d5a94b68@gmail.com> Date: Tue, 22 Oct 2024 17:14:33 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC To: Miquel Raynal Cc: richard@nod.at, vigneshr@ti.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nikita.shubin@maquefel.me, arnd@arndb.de, vkoul@kernel.org, esben@geanix.com, linux-arm-kernel@lists.infradead.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241018022519.721914-1-hpchen0nvt@gmail.com> <20241018022519.721914-3-hpchen0nvt@gmail.com> <20241021103254.1f31205b@xps-13> <9cfd923a-4bc8-4a6c-986d-8d0c6fd6d9bb@gmail.com> <20241022105109.1906f524@xps-13> Content-Language: en-US From: Hui-Ping Chen In-Reply-To: <20241022105109.1906f524@xps-13> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Dear Miquel, Thank you for your reply. On 2024/10/22 下午 04:51, Miquel Raynal wrote: > Hi Hui-Ping, > >>>> + >>>> +static int ma35_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf, >>>> + int oob_required, int page) >>>> +{ >>> The hardware ECC engine should always be disabled by default. >>> >>> Then, in these helpers you should: >>> * enable the ECC engine >>> * do your things >>> * disable the ECC engine >> The ECC engine of the MA35 NAND controller cannot be turned on or off separately. >> >> The ECC engine is activated with the DMA, >> >> and it calculates and writes to the OOB during the transfer. > What about: > > ECC Algorithm Enable Bit [23] ECCEN > > This field is used to select the ECC algorithm for data > protecting. The BCH algorithm can correct 8 or 12 or 24 bits. > 0 = BCH code encode/decode Disabled. > 1 = BCH code encode/decode Enabled. > > ? That's right, this bit represents this meaning, but ECC operations will only occur when DMA is activated. I will add enable/disable ECC engine before and after reading/writing the page. > Thanks, > Miquèl Best regards, Hui-Ping Chen