From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE187C07E99 for ; Mon, 12 Jul 2021 03:41:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B31F961004 for ; Mon, 12 Jul 2021 03:41:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229998AbhGLDo1 (ORCPT ); Sun, 11 Jul 2021 23:44:27 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:47586 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232507AbhGLDo1 (ORCPT ); Sun, 11 Jul 2021 23:44:27 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1626061299; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=hs7Tqld0fBRwacaQc2I/5U3RxF7nEO0L5nh1M+lL7NQ=; b=FWfWyQXsi7NB94jvzV+Nf1UB8MFLnBFPd7p47PS1PDeAmIVjAz8naDoEErcPVKfJ+tloTSUt Ed5offP7riSF2nMpTV5cTluhGc7/bHDYvrS5t2Msgno1wm2JjyhuYVz7ksJs+9k7Ij6HxZwL 8vsVInBPgWFarhCUpUmygZF55A8= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-east-1.postgun.com with SMTP id 60ebb9ec7b2963a2828d7af4 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 12 Jul 2021 03:41:32 GMT Sender: saiprakash.ranjan=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 06508C4338A; Mon, 12 Jul 2021 03:41:32 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 12B2AC433F1; Mon, 12 Jul 2021 03:41:31 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 12 Jul 2021 09:11:30 +0530 From: Sai Prakash Ranjan To: Kalyan Thota Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robdclark@gmail.com, dianders@chromium.org, mkrishn@codeaurora.org, rnayak@codeaurora.org Subject: Re: [v1] drm/msm/disp/dpu1: add safe lut config in dpu driver In-Reply-To: <1625827244-23274-1-git-send-email-kalyan_t@codeaurora.org> References: <1625827244-23274-1-git-send-email-kalyan_t@codeaurora.org> Message-ID: <38beafdc174cbb16de6f1d646fff6816@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2021-07-09 16:10, Kalyan Thota wrote: > Add safe lut configuration for all the targets in dpu > driver as per QOS recommendation. > > Issue reported on SC7280: > > With wait-for-safe feature in smmu enabled, RT client > buffer levels are checked to be safe before smmu invalidation. > Since display was always set to unsafe it was delaying the > invalidaiton process thus impacting the performance on NRT clients > such as eMMC and NVMe. > > Validated this change on SC7280, With this change eMMC performance > has improved significantly. > > Signed-off-by: Kalyan Thota > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index d01c4c9..2e482cd 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -974,6 +974,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = > { > .amortizable_threshold = 25, > .min_prefill_lines = 24, > .danger_lut_tbl = {0xf, 0xffff, 0x0}, > + .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sdm845_qos_linear), > .entries = sdm845_qos_linear > @@ -1001,6 +1002,7 @@ static const struct dpu_perf_cfg sc7180_perf_data > = { > .min_dram_ib = 1600000, > .min_prefill_lines = 24, > .danger_lut_tbl = {0xff, 0xffff, 0x0}, > + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sc7180_qos_linear), > .entries = sc7180_qos_linear > @@ -1028,6 +1030,7 @@ static const struct dpu_perf_cfg sm8150_perf_data > = { > .min_dram_ib = 800000, > .min_prefill_lines = 24, > .danger_lut_tbl = {0xf, 0xffff, 0x0}, > + .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sm8150_qos_linear), > .entries = sm8150_qos_linear > @@ -1056,6 +1059,7 @@ static const struct dpu_perf_cfg sm8250_perf_data > = { > .min_dram_ib = 800000, > .min_prefill_lines = 35, > .danger_lut_tbl = {0xf, 0xffff, 0x0}, > + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sc7180_qos_linear), > .entries = sc7180_qos_linear > @@ -1084,6 +1088,7 @@ static const struct dpu_perf_cfg sc7280_perf_data > = { > .min_dram_ib = 1600000, > .min_prefill_lines = 24, > .danger_lut_tbl = {0xffff, 0xffff, 0x0}, > + .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), > .entries = sc7180_qos_macrotile Tested-by: Sai Prakash Ranjan (sc7280, sc7180) This will need fixes and stable tag and I think this should also fix the wait-for-safe issue with sdm845 (ufs/usb speed slowdown with display active) which we have in arm-smmu-qcom. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation