From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6C2A223DDC; Mon, 19 May 2025 06:07:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747634832; cv=none; b=GZritnfg2gCEoFhB3crsBrqkInol6SdegEAeuWC5widr97QYqCQqUkE2WYLIl5XQ7RZohQUUSZLbLjM43ml1zuVGIl39/Dl6zRC/K4mASP9NJ1Z5bYgs47r8c/S/bQdPDCFzD3rc2nD1dh93fOkFUrt0AsRHpu5G+jCArE5BKOw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747634832; c=relaxed/simple; bh=mzBMq3RddGmQcxuRxndTk8lILd7AX2RNmDvdUcdMMK4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=rBdgTQI1oTyiaK+bMBo8lDFiPOWXwh8/FXML94ln+oirOavWw1vfJzejjMOJaI+zPHo/uyZE5OifedwtT7mQE5qY4/Ds3BB62cU99NQ+Sh2mEoyHGjoKoCMGcEI8zQanribN16ITEP5ErOW52bYSXX/pli7TN6kbZuGAVZC5OI8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vz+gRGtD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vz+gRGtD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 13800C4CEE4; Mon, 19 May 2025 06:07:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747634830; bh=mzBMq3RddGmQcxuRxndTk8lILd7AX2RNmDvdUcdMMK4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Vz+gRGtDt6VGed2bxqKSTa24v11F/DvLPQWge23acgb7OGQkUW5WeTEIPixRdt4dg xB9qeCZKX8ioISOIS5G077S4ovErXGkrP6FAqIJyHVnKXDl3t0ASnpcaTLOOdNMESZ bQexZlAkZgFsCobmh1IbVGSQ9tVjuRyFmuWro0aCQDZbYNmSknpjOP3riAXhLbeAmx MOV/AKQPQMAro41bYbjJLDFgtKmXSDHkcx/PkilaDf3lpeQm7gHWELN9q3Zj5FRCN5 zwIRzegP8Z+xTwXdG3LdGwAyJ5M6wySkdTB/BDKDvcLy53g9WdGjvuM+9LzPN5ac69 NYHD558nOSHMQ== Message-ID: <3942413e-bbc0-4320-92ef-4a84b19dece2@kernel.org> Date: Mon, 19 May 2025 08:07:03 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 01/10] dt-bindings: npu: rockchip,rknn: Add bindings To: Tomeu Vizoso , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Oded Gabbay , Jonathan Corbet , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sumit Semwal , =?UTF-8?Q?Christian_K=C3=B6nig?= , Sebastian Reichel , Nicolas Frattaroli , Jeff Hugo Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org References: <20250516-6-10-rocket-v3-0-7051ac9225db@tomeuvizoso.net> <20250516-6-10-rocket-v3-1-7051ac9225db@tomeuvizoso.net> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 16/05/2025 18:53, Tomeu Vizoso wrote: > Add the bindings for the Neural Processing Unit IP from Rockchip. > > v2: > - Adapt to new node structure (one node per core, each with its own > IOMMU) > - Several misc. fixes from Sebastian Reichel > > v3: > - Split register block in its constituent subblocks, and only require > the ones that the kernel would ever use (Nicolas Frattaroli) > - Group supplies (Rob Herring) > - Explain the way in which the top core is special (Rob Herring) > > Signed-off-by: Tomeu Vizoso > Signed-off-by: Sebastian Reichel > --- > .../bindings/npu/rockchip,rknn-core.yaml | 162 +++++++++++++++++++++ Nothing here was tested, so limited review. > 1 file changed, 162 insertions(+) > > diff --git a/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..4572fb777f1454d0147da29791033fc27c53b8d2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml > @@ -0,0 +1,162 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/npu/rockchip,rknn-core.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Neural Processing Unit IP from Rockchip > + > +maintainers: > + - Tomeu Vizoso > + > +description: > + Rockchip IP for accelerating inference of neural networks, based on NVIDIA's > + open source NVDLA IP. > + > + There is to be a node per each core in the NPU. In Rockchip's design there > + will be one core that is special and needs to be powered on before any of the > + other cores can be used. This special core is called the top core and should > + have the compatible string that corresponds to top cores. > + > +properties: > + $nodename: > + pattern: '^npu-core@[a-f0-9]+$' > + > + compatible: > + oneOf: > + - items: Drop, just enum > + - enum: > + - rockchip,rk3588-rknn-core-top > + - items: Drop > + - enum: Drop, part of previous enum. > + - rockchip,rk3588-rknn-core > + > + reg: > + minItems: 3 No, maxItems instead > + > + reg-names: > + minItems: 3 No, drop, makes no sense. > + items: > + - const: pc > + - const: cna > + - const: core > + > + clocks: > + minItems: 2 > + maxItems: 4 > + > + clock-names: > + items: > + - const: aclk > + - const: hclk > + - const: npu > + - const: pclk > + minItems: 2 > + > + interrupts: > + maxItems: 1 > + > + iommus: > + maxItems: 1 > + > + npu-supply: true > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 2 > + > + reset-names: > + items: > + - const: srst_a > + - const: srst_h > + > + sram-supply: true > + > +required: > + - compatible > + - reg reg-names > + - clocks > + - clock-names > + - interrupts > + - iommus > + - power-domains > + - resets > + - reset-names > + - npu-supply > + - sram-supply > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - rockchip,rknn-core-top > + then: > + properties: > + clocks: > + minItems: 4 > + > + clock-names: > + minItems: 4 > + - if: > + properties: > + compatible: > + contains: > + enum: > + - rockchip,rknn-core > + then: > + properties: > + clocks: > + maxItems: 2 > + clock-names: > + maxItems: 2 > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + rknn_core_top: npu-core@fdab0000 { Drop unused label npu@ > + compatible = "rockchip,rk3588-rknn-core-top", "rockchip,rknn-core-top"; This makes no sense... If you change compatibles you must change example DTS and your DTS. > + reg = <0x0 0xfdab0000 0x0 0x9000>; > + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; > + assigned-clock-rates = <200000000>; > + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, > + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; > + clock-names = "aclk", "hclk", "npu", "pclk"; > + interrupts = ; > + iommus = <&rknn_mmu_top>; > + npu-supply = <&vdd_npu_s0>; > + power-domains = <&power RK3588_PD_NPUTOP>; > + resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>; > + reset-names = "srst_a", "srst_h"; > + sram-supply = <&vdd_npu_mem_s0>; > + }; > + > + rknn_core_1: npu-core@fdac0000 { > + compatible = "rockchip,rk3588-rknn-core", "rockchip,rknn-core"; > + reg = <0x0 0xfdac0000 0x0 0x9000>; > + clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; Difference by one property does not really justify new example. Keep only one, which would halve the errors you have here. :/ Best regards, Krzysztof