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Sun, 25 May 2025 15:33:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1748179993; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iaBe/qc+2pXExuQttHiqmVdIlwW/IMB18Yyn98zdkjY=; b=WvmTCjqShVbX7JrLS/FXF6KbBbigWBeZGBKazdmn4NQK4CkL1ptA5YNgySTl/lA0pSg5/w QygXSca6z+l22SB8KD1QuTVtOQXIC+wPFHCisYCeO0PZi1jfAby75/4uVNKv0wsSkFG8Y2 1eTA1YmIPUnZjSqtiUI8o1wrjRWYjFF4nCcLjxfhD4FvPz6PXzE4fBZShIpDt+SoyWgTaY gTvIX15B/TcDUn98ZtzvMV1eWyxD6lGiMhUgscoYNfRlABPBd5i8uEuYwXC2ykokgCYnYg L4KZ6ERAizdr7FjmrFliBo5MtkdKSwh28mNRG0ccxno57oRpdHSFOA9rjiX+iA== Message-ID: <395343ba-93cc-495c-b5eb-7ee425996465@mailbox.org> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1748179991; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iaBe/qc+2pXExuQttHiqmVdIlwW/IMB18Yyn98zdkjY=; b=D0Achqh8/WvHVdwyXE9o848j56o/juRstx9hORCoSrgA/Fn/HCpZGhVu4/hhga2/zbptuB Dobf0+K909nOZlzOh7y+j9hRFVyq9X5ppmZEkvP2TLfk7Y5pt23y8GpbJjY7zJW9OAAt55 SMlWRjUBbCJBkpg1NXf+MUFqmO8mrp9zzpWzXh0s4UNFwRZQ0cmn9XtA80kSE6hFQh8Zj6 F0ysGSEoa68rDaZecgqkwRSxyqrQtXfnjiOcmQV9QSif8nsTy1hNny7OvpJZfC6EdiJhkf UEfQt70cWDx90X/dghI98D7RfbMRkqGL95vzgEE/t8GAJanxT0tvp9FIZB37eA== Date: Sun, 25 May 2025 15:33:05 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document optional aux clock To: Geert Uytterhoeven Cc: Rob Herring , Marek Vasut , linux-arm-kernel@lists.infradead.org, =?UTF-8?Q?Niklas_S=C3=B6derlund?= , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , Aradhya Bhatia , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Junhao Xie , Kever Yang , Krzysztof Kozlowski , Kuninori Morimoto , Lorenzo Pieralisi , Magnus Damm , Manivannan Sadhasivam , Neil Armstrong , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org References: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> <20250406144822.21784-2-marek.vasut+renesas@mailbox.org> <20250410204845.GA1027003-robh@kernel.org> <40c400ab-8770-4595-9a4c-004e6157c348@mailbox.org> Content-Language: en-US From: Marek Vasut In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-MBO-RS-ID: 30e54f29d21d2aff1b6 X-MBO-RS-META: 3hum87jao36mwgujkt91b8to163zmxcp On 4/23/25 11:38 AM, Geert Uytterhoeven wrote: > Hi Marek, Hi, > On Sun, 13 Apr 2025 at 11:29, Marek Vasut wrote: >> On 4/10/25 10:48 PM, Rob Herring wrote: >>> On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote: >>>> Document 'aux' clock which are used to supply the PCIe bus. This >>>> is useful in case of a hardware setup, where the PCIe controller >>>> input clock and the PCIe bus clock are supplied from the same >>>> clock synthesiser, but from different differential clock outputs: >>>> >>>> ____________ _____________ >>>> | R-Car PCIe | | PCIe device | >>>> | | | | >>>> | PCIe RX<|==================|>PCIe TX | >>>> | PCIe TX<|==================|>PCIe RX | >>>> | | | | >>>> | PCIe CLK<|======.. ..======|>PCIe CLK | >>>> '------------' || || '-------------' >>>> || || >>>> ____________ || || >>>> | 9FGV0441 | || || >>>> | | || || >>>> | CLK DIF0<|======'' || >>>> | CLK DIF1<|=========='' >>>> | CLK DIF2<| >>>> | CLK DIF3<| >>>> '------------' >>>> >>>> The clock are named 'aux' because those are one of the clock listed in >>>> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which >>>> fit closest to the PCIe bus clock. According to that binding document, >>>> the 'aux' clock describe clock which supply the PMC domain, which is >>>> likely PCIe Mezzanine Card domain. >>> >>> Pretty sure that PMC is "power management controller" given it talks >>> about low power states. >>> >>> >>>> >>>> Tested-by: Niklas Söderlund >>>> Signed-off-by: Marek Vasut >>>> --- >>>> NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml >>>> instead and add 'bus' clock outright ? >>> >>> Based on the diagram, this has nothing to do with the specific >>> controller. It should also probably a root port property, not host >>> bridge. >> How would you suggest I describe the clock which supply the PCIe bus >> clock lane (CLK DIF1 in the diagram) , which have to be enabled together >> with clock which supply the PCIe controller input clock lane (CLK DIF0) ? > > I think Rob wants you to add clocks/clock-names for this to > dtschema/schemas/pci/pci-bus-common.yaml. Then you can have pcie@M,N > subnode(s) with num-lanes, clock, and clock-names describing the PCIe > endpoint(s)? > > git grep "pcie*@[0-9],[0-9]" -- $(git grep -l num-lanes -- Documentation/ ) > > Does that make sense? No, not really. There can be any arbitrary PCIe card plugged into the M.2 slot, so how can I predict what exactly will be plugged into the slot and describe it in DT up front this way ? -- Best regards, Marek Vasut