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Fri, 24 Jul 2026 00:44:17 -0700 (PDT) X-Received: by 2002:a05:6a00:278d:b0:848:2e3c:9955 with SMTP id d2e1a72fcca58-84e2b82f7c2mr6728943b3a.4.1784879057049; Fri, 24 Jul 2026 00:44:17 -0700 (PDT) Received: from [10.218.5.114] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84e17578345sm4194987b3a.39.2026.07.24.00.44.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 00:44:16 -0700 (PDT) Message-ID: <39718bb3-8f13-4cfa-946a-908eeff0653e@oss.qualcomm.com> Date: Fri, 24 Jul 2026 13:12:33 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/4] clk: qcom: common: Register reset controller only when resets are present To: sashiko-reviews@lists.linux.dev Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org References: <20260723-shikra-audiocorecc-v3-0-90b878ae0d4e@oss.qualcomm.com> <20260723-shikra-audiocorecc-v3-1-90b878ae0d4e@oss.qualcomm.com> <20260723155515.68A0E1F00A3A@smtp.kernel.org> Content-Language: en-US From: Imran Shaik In-Reply-To: <20260723155515.68A0E1F00A3A@smtp.kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA2OSBTYWx0ZWRfX+1tnRvgj9vPb FCBh5UzLuCXBxkEWRN881G7sbm32IMQPcL2K+hwqABHt2aF7PKrUjSH3KmU/eKPe9oqSUINFvIL zCeX2Cdfk5T+qYji3yvhgYRh5cwILbavrK7myAWa53HPFxyDlltkKfA9JvlrIekHs7OHQq4LMHn 9MoVAJYrK+YB6fzwD1BDf0c7HrHuYUFkse1Q5t1Zr+po5tspmhzFCvSc2a4mbkYvSrW8w05CX2X yaZQwE6GENkfIHFFZWfISsNVXbTEJ2BDqCG8Qu5YAkD2/2qCh2vvB96Iu6exTy44xDcoG73RYki UzOPWGDhyW0Shn6FiyVHImFPZgrTYZcrzzGMHZ8E2mapMKUK0TJAng+/GAzd5AQIUxSyIDZOW+8 9ydAMsN9oBD/tmadXXHjwNyg4Myhxa3fD5JX87X3L/hHcHbGGKvN+P2HJm+5gL0foOuGbBwDaCJ BX9sktH8r7JoKDq87BA== X-Proofpoint-GUID: 2lPApJd1WA7DSLpFZK10uEngXyB3R1xa X-Authority-Analysis: v=2.4 cv=DfAnbPtW c=1 sm=1 tr=0 ts=6a6317d2 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Z0OJ9TEZ1dYWzG6c7Z0A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA2OSBTYWx0ZWRfX48Y/hpEvUc2V IQ308ODf3jrNA23hBFRaOajMLSjnHWpopGrm9V5gMhX/TOEsykm44K5GXJg/RyTOkssC7Z1PyPN TT/oprr+LeZXza+pR8DIFFzoBsxT5hI= X-Proofpoint-ORIG-GUID: 2lPApJd1WA7DSLpFZK10uEngXyB3R1xa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240069 On 23-07-2026 09:25 pm, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [High] The local pointer `reset` is used uninitialized when registering GDSCs if the clock controller defines GDSCs but no resets. > -- > > --- Patch [1]: [PATCH v3 1/4] clk: qcom: common: Register reset controller only when resets are present --- > commit 4dacf2df1c1e317705833daaa92c7514eab60f24 > Author: Imran Shaik > > clk: qcom: common: Register reset controller only when resets are present > > This commit avoids registering a reset controller if the clock controller > descriptor does not define any resets. It does this by checking if > desc->num_resets is non-zero before initializing and registering the > controller. > >> diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c >> --- a/drivers/clk/qcom/common.c >> +++ b/drivers/clk/qcom/common.c > [ ... ] >> @@ -359,17 +359,19 @@ int qcom_cc_really_probe(struct device *dev, >> qcom_cc_clk_regs_configure(dev, desc->driver_data, regmap); >> } >> >> - reset = &cc->reset; >> - reset->rcdev.of_node = dev->of_node; >> - reset->rcdev.ops = &qcom_reset_ops; >> - reset->rcdev.owner = dev->driver->owner; >> - reset->rcdev.nr_resets = desc->num_resets; >> - reset->regmap = regmap; >> - reset->reset_map = desc->resets; >> - >> - ret = devm_reset_controller_register(dev, &reset->rcdev); >> - if (ret) >> - goto put_rpm; >> + if (desc->num_resets) { >> + reset = &cc->reset; >> + reset->rcdev.of_node = dev->of_node; >> + reset->rcdev.ops = &qcom_reset_ops; >> + reset->rcdev.owner = dev->driver->owner; >> + reset->rcdev.nr_resets = desc->num_resets; >> + reset->regmap = regmap; >> + reset->reset_map = desc->resets; >> + >> + ret = devm_reset_controller_register(dev, &reset->rcdev); >> + if (ret) >> + goto put_rpm; >> + } >> >> if (desc->gdscs && desc->num_gdscs) { >> scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); >> if (!scd) { >> ret = -ENOMEM; >> goto put_rpm; >> } >> scd->dev = dev; >> scd->scs = desc->gdscs; >> scd->num = desc->num_gdscs; >> scd->pd_list = cc->pd_list; >> ret = gdsc_register(scd, &reset->rcdev, regmap); > > [Severity: High] > If a clock controller defines GDSCs but no resets, does this leave the reset > pointer uninitialized when evaluated here? > > During qcom_cc_really_probe(), the new if (desc->num_resets) block skips the > initialization of the reset pointer when the clock controller has no resets > defined. > > However, the pointer arithmetic &reset->rcdev is still evaluated when > calling gdsc_register(). Passing this uninitialized garbage address could invoke > undefined behavior and cause a panic during boot when compiler hardening tools > are enabled. > This appears to be a valid issue. I will check further and submit the updated changes in a separate patch. For now, I'll drop this change from this series, as it is no longer required after separating AudioCoreCC clocks and resets into different devices. Thanks, Imran