* [PATCH 0/2] Add support for Agilex3 SoCFPGA board @ 2025-11-10 6:47 niravkumarlaxmidas.rabara 2025-11-10 6:47 ` [PATCH 1/2] dt-bindings: intel: Add " niravkumarlaxmidas.rabara 2025-11-10 6:47 ` [PATCH 2/2] arm64: dts: socfpga: add Agilex3 board niravkumarlaxmidas.rabara 0 siblings, 2 replies; 8+ messages in thread From: niravkumarlaxmidas.rabara @ 2025-11-10 6:47 UTC (permalink / raw) To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel Cc: Niravkumar L Rabara From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> Agilex3 SoCFPGA development kit is a low cost and small form factor development kit similar to Agilex5 013b board. Agilex3 SoCFPGA is derived from Agilex5 SoCFPGA, with the main difference being the number of CPU cores — Agilex3 has 2 cores compared to 4 in Agilex5. https://www.altera.com/products/devkit/a1jui000005pw9bmas/agilex-3-fpga-and-soc-c-series-development-kit This series includes: - The addition of the Agilex3 compatible in DT bindings. - The initial board device tree support for the Agilex3 SoCFPGA. Note: The patch 2 depends on the series: "Add iommu supports" https://lore.kernel.org/all/cover.1760486497.git.khairul.anuar.romli@altera.com/ Patch series "Add iommu supports" is applied to socfpga maintainer's tree https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 Niravkumar L Rabara (2): dt-bindings: intel: Add Agilex3 SoCFPGA board arm64: dts: socfpga: add Agilex3 board .../bindings/arm/intel,socfpga.yaml | 5 + arch/arm64/boot/dts/intel/Makefile | 1 + .../boot/dts/intel/socfpga_agilex3_socdk.dts | 130 ++++++++++++++++++ 3 files changed, 136 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts -- 2.25.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] dt-bindings: intel: Add Agilex3 SoCFPGA board 2025-11-10 6:47 [PATCH 0/2] Add support for Agilex3 SoCFPGA board niravkumarlaxmidas.rabara @ 2025-11-10 6:47 ` niravkumarlaxmidas.rabara 2025-11-10 7:53 ` Krzysztof Kozlowski 2025-11-10 6:47 ` [PATCH 2/2] arm64: dts: socfpga: add Agilex3 board niravkumarlaxmidas.rabara 1 sibling, 1 reply; 8+ messages in thread From: niravkumarlaxmidas.rabara @ 2025-11-10 6:47 UTC (permalink / raw) To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel Cc: Niravkumar L Rabara From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> Add compatible for Agilex3 SoCFPGA board. Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index cf7a91dfec8a..e706c4eff019 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -21,6 +21,11 @@ properties: - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - const: intel,socfpga-agilex + - description: Agilex3 boards + items: + - enum: + - intel,socfpga-agilex3-socdk + - const: intel,socfpga-agilex5 - description: Agilex5 boards items: - enum: -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: intel: Add Agilex3 SoCFPGA board 2025-11-10 6:47 ` [PATCH 1/2] dt-bindings: intel: Add " niravkumarlaxmidas.rabara @ 2025-11-10 7:53 ` Krzysztof Kozlowski 2025-11-10 12:36 ` Dinh Nguyen 0 siblings, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2025-11-10 7:53 UTC (permalink / raw) To: niravkumarlaxmidas.rabara, Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel On 10/11/2025 07:47, niravkumarlaxmidas.rabara@altera.com wrote: > From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> > > Add compatible for Agilex3 SoCFPGA board. > > Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> > --- > Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml > index cf7a91dfec8a..e706c4eff019 100644 > --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml > +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml > @@ -21,6 +21,11 @@ properties: > - intel,socfpga-agilex-n6000 > - intel,socfpga-agilex-socdk > - const: intel,socfpga-agilex > + - description: Agilex3 boards Agilex3? > + items: > + - enum: > + - intel,socfpga-agilex3-socdk > + - const: intel,socfpga-agilex5 Or Agilex5? Decide. Cannot be both. > - description: Agilex5 boards> items: > - enum: Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: intel: Add Agilex3 SoCFPGA board 2025-11-10 7:53 ` Krzysztof Kozlowski @ 2025-11-10 12:36 ` Dinh Nguyen 2025-11-10 12:38 ` Krzysztof Kozlowski 0 siblings, 1 reply; 8+ messages in thread From: Dinh Nguyen @ 2025-11-10 12:36 UTC (permalink / raw) To: Krzysztof Kozlowski, niravkumarlaxmidas.rabara, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel On 11/10/25 01:53, Krzysztof Kozlowski wrote: > On 10/11/2025 07:47, niravkumarlaxmidas.rabara@altera.com wrote: >> From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> >> >> Add compatible for Agilex3 SoCFPGA board. >> >> Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> >> --- >> Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml >> index cf7a91dfec8a..e706c4eff019 100644 >> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml >> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml >> @@ -21,6 +21,11 @@ properties: >> - intel,socfpga-agilex-n6000 >> - intel,socfpga-agilex-socdk >> - const: intel,socfpga-agilex >> + - description: Agilex3 boards > > Agilex3? > From what I understand, the Agilex3 is the same chip as the Agilex5, minus 2 CPU cores. So I recommended to Nirav, just to add the binding in the Agilex5 context. >> + items: >> + - enum: >> + - intel,socfpga-agilex3-socdk >> + - const: intel,socfpga-agilex5 > > Or Agilex5? Decide. Cannot be both. > From the explanation above, could we document the agilex3 socdk this way? Thanks, Dinh ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: intel: Add Agilex3 SoCFPGA board 2025-11-10 12:36 ` Dinh Nguyen @ 2025-11-10 12:38 ` Krzysztof Kozlowski 0 siblings, 0 replies; 8+ messages in thread From: Krzysztof Kozlowski @ 2025-11-10 12:38 UTC (permalink / raw) To: Dinh Nguyen, niravkumarlaxmidas.rabara, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel On 10/11/2025 13:36, Dinh Nguyen wrote: > > > On 11/10/25 01:53, Krzysztof Kozlowski wrote: >> On 10/11/2025 07:47, niravkumarlaxmidas.rabara@altera.com wrote: >>> From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> >>> >>> Add compatible for Agilex3 SoCFPGA board. > >>> >>> Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> >>> --- >>> Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++ >>> 1 file changed, 5 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml >>> index cf7a91dfec8a..e706c4eff019 100644 >>> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml >>> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml >>> @@ -21,6 +21,11 @@ properties: >>> - intel,socfpga-agilex-n6000 >>> - intel,socfpga-agilex-socdk >>> - const: intel,socfpga-agilex >>> + - description: Agilex3 boards >> >> Agilex3? >> > > From what I understand, the Agilex3 is the same chip as the Agilex5, > minus 2 CPU cores. So I recommended to Nirav, just to add the binding in > the Agilex5 context. If that is not the same die, then probably should have still agilex3 compatible (you still can have fallback). > >>> + items: >>> + - enum: >>> + - intel,socfpga-agilex3-socdk >>> + - const: intel,socfpga-agilex5 >> >> Or Agilex5? Decide. Cannot be both. >> > From the explanation above, could we document the agilex3 socdk this way? > > Thanks, > Dinh Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] arm64: dts: socfpga: add Agilex3 board 2025-11-10 6:47 [PATCH 0/2] Add support for Agilex3 SoCFPGA board niravkumarlaxmidas.rabara 2025-11-10 6:47 ` [PATCH 1/2] dt-bindings: intel: Add " niravkumarlaxmidas.rabara @ 2025-11-10 6:47 ` niravkumarlaxmidas.rabara 2025-11-10 12:37 ` Dinh Nguyen 1 sibling, 1 reply; 8+ messages in thread From: niravkumarlaxmidas.rabara @ 2025-11-10 6:47 UTC (permalink / raw) To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel Cc: Niravkumar L Rabara From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> Agilex3 SoCFPGA development kit is a small form factor board similar to Agilex5 013b board. Agilex3 SoCFPGA is derived from Agilex5 SoCFPGA, with the main difference of CPU cores — Agilex3 has 2 cores compared to 4 in Agilex5. Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> --- Note: This patch depends on the series: "Add iommu supports" https://lore.kernel.org/all/cover.1760486497.git.khairul.anuar.romli@altera.com/ Patch series "Add iommu supports" is applied to socfpga maintainer's tree https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 arch/arm64/boot/dts/intel/Makefile | 1 + .../boot/dts/intel/socfpga_agilex3_socdk.dts | 130 ++++++++++++++++++ 2 files changed, 131 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 391d5cbe50b3..a117268267ee 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ + socfpga_agilex3_socdk.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex5_socdk_013b.dtb \ socfpga_agilex5_socdk_nand.dtb \ diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts new file mode 100644 index 000000000000..3280bdd49faa --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, Altera Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex3 SoCDK"; + compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "hps_led0"; + gpios = <&porta 1 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&porta 12 GPIO_ACTIVE_HIGH>; + }; + + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + rxc-skew-ps = <0>; + rxdv-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <0>; + txen-skew-ps = <60>; + txd0-skew-ps = <60>; + txd1-skew-ps = <60>; + txd2-skew-ps = <60>; + txd3-skew-ps = <60>; + }; + }; +}; + +/delete-node/ &cpu2; + +/delete-node/ &cpu3; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x00600000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x00600000 0x03a00000>; + }; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] arm64: dts: socfpga: add Agilex3 board 2025-11-10 6:47 ` [PATCH 2/2] arm64: dts: socfpga: add Agilex3 board niravkumarlaxmidas.rabara @ 2025-11-10 12:37 ` Dinh Nguyen 2025-11-11 2:22 ` Niravkumar L Rabara 0 siblings, 1 reply; 8+ messages in thread From: Dinh Nguyen @ 2025-11-10 12:37 UTC (permalink / raw) To: niravkumarlaxmidas.rabara, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel On 11/10/25 00:47, niravkumarlaxmidas.rabara@altera.com wrote: > From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> > > Agilex3 SoCFPGA development kit is a small form factor board similar to > Agilex5 013b board. > Agilex3 SoCFPGA is derived from Agilex5 SoCFPGA, with the main difference > of CPU cores — Agilex3 has 2 cores compared to 4 in Agilex5. > > Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> > --- > Note: > This patch depends on the series: "Add iommu supports" > https://lore.kernel.org/all/cover.1760486497.git.khairul.anuar.romli@altera.com/ > > Patch series "Add iommu supports" is applied to socfpga maintainer's tree > https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 > > arch/arm64/boot/dts/intel/Makefile | 1 + > .../boot/dts/intel/socfpga_agilex3_socdk.dts | 130 ++++++++++++++++++ > 2 files changed, 131 insertions(+) > create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts > > diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile > index 391d5cbe50b3..a117268267ee 100644 > --- a/arch/arm64/boot/dts/intel/Makefile > +++ b/arch/arm64/boot/dts/intel/Makefile > @@ -2,6 +2,7 @@ > dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ > socfpga_agilex_socdk.dtb \ > socfpga_agilex_socdk_nand.dtb \ > + socfpga_agilex3_socdk.dtb \ > socfpga_agilex5_socdk.dtb \ > socfpga_agilex5_socdk_013b.dtb \ > socfpga_agilex5_socdk_nand.dtb \ > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts > new file mode 100644 > index 000000000000..3280bdd49faa > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts > @@ -0,0 +1,130 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2025, Altera Corporation > + */ > +#include "socfpga_agilex5.dtsi" > + > +/ { > + model = "SoCFPGA Agilex3 SoCDK"; > + compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex5"; > + > + aliases { > + serial0 = &uart0; > + ethernet2 = &gmac2; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + leds { > + compatible = "gpio-leds"; > + > + led0 { > + label = "hps_led0"; > + gpios = <&porta 1 GPIO_ACTIVE_HIGH>; > + }; > + > + led1 { > + label = "hps_led1"; > + gpios = <&porta 12 GPIO_ACTIVE_HIGH>; > + }; > + > + }; You need the : cpus { /delete-node/ cpu@2; /delete-node/ cpu@3; }; Dinh ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] arm64: dts: socfpga: add Agilex3 board 2025-11-10 12:37 ` Dinh Nguyen @ 2025-11-11 2:22 ` Niravkumar L Rabara 0 siblings, 0 replies; 8+ messages in thread From: Niravkumar L Rabara @ 2025-11-11 2:22 UTC (permalink / raw) To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel On 10/11/2025 8:37 pm, Dinh Nguyen wrote: > > > On 11/10/25 00:47, niravkumarlaxmidas.rabara@altera.com wrote: >> From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> >> >> Agilex3 SoCFPGA development kit is a small form factor board similar to >> Agilex5 013b board. >> Agilex3 SoCFPGA is derived from Agilex5 SoCFPGA, with the main difference >> of CPU cores — Agilex3 has 2 cores compared to 4 in Agilex5. >> >> Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> >> --- >> Note: >> This patch depends on the series: "Add iommu supports" >> https://lore.kernel.org/all/ >> cover.1760486497.git.khairul.anuar.romli@altera.com/ >> >> Patch series "Add iommu supports" is applied to socfpga maintainer's tree >> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/ >> log/?h=socfpga_dts_for_v6.19 >> >> arch/arm64/boot/dts/intel/Makefile | 1 + >> .../boot/dts/intel/socfpga_agilex3_socdk.dts | 130 ++++++++++++++++++ >> 2 files changed, 131 insertions(+) >> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts >> >> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/ >> intel/Makefile >> index 391d5cbe50b3..a117268267ee 100644 >> --- a/arch/arm64/boot/dts/intel/Makefile >> +++ b/arch/arm64/boot/dts/intel/Makefile >> @@ -2,6 +2,7 @@ >> dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ >> socfpga_agilex_socdk.dtb \ >> socfpga_agilex_socdk_nand.dtb \ >> + socfpga_agilex3_socdk.dtb \ >> socfpga_agilex5_socdk.dtb \ >> socfpga_agilex5_socdk_013b.dtb \ >> socfpga_agilex5_socdk_nand.dtb \ >> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/ >> arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts >> new file mode 100644 >> index 000000000000..3280bdd49faa >> --- /dev/null >> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts >> @@ -0,0 +1,130 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (C) 2025, Altera Corporation >> + */ >> +#include "socfpga_agilex5.dtsi" >> + >> +/ { >> + model = "SoCFPGA Agilex3 SoCDK"; >> + compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex5"; >> + >> + aliases { >> + serial0 = &uart0; >> + ethernet2 = &gmac2; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> + >> + leds { >> + compatible = "gpio-leds"; >> + >> + led0 { >> + label = "hps_led0"; >> + gpios = <&porta 1 GPIO_ACTIVE_HIGH>; >> + }; >> + >> + led1 { >> + label = "hps_led1"; >> + gpios = <&porta 12 GPIO_ACTIVE_HIGH>; >> + }; >> + >> + }; > > You need the : > > cpus { > /delete-node/ cpu@2; > /delete-node/ cpu@3; > }; > > > Dinh I tried this way Dinh, but it doesn't work in dts, compile gives error. /delete-node/ cpu@2; /delete-node/ cpu@3; works correctly. Anyway I will send v2 patch with a socfpga_agilex3.dtsi for Agilex3 silicon which include "socfpga_agilex5.dtsi" and delete the cpu2 and cpu3 in dtsi file instead of dts. Thanks, Nirav ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-11-11 2:22 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-11-10 6:47 [PATCH 0/2] Add support for Agilex3 SoCFPGA board niravkumarlaxmidas.rabara 2025-11-10 6:47 ` [PATCH 1/2] dt-bindings: intel: Add " niravkumarlaxmidas.rabara 2025-11-10 7:53 ` Krzysztof Kozlowski 2025-11-10 12:36 ` Dinh Nguyen 2025-11-10 12:38 ` Krzysztof Kozlowski 2025-11-10 6:47 ` [PATCH 2/2] arm64: dts: socfpga: add Agilex3 board niravkumarlaxmidas.rabara 2025-11-10 12:37 ` Dinh Nguyen 2025-11-11 2:22 ` Niravkumar L Rabara
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).