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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e12-20020ac2546c000000b004ca0ea7af24sm2909772lfn.174.2023.01.11.13.52.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 13:52:40 -0800 (PST) Message-ID: <39c01d7b-eee4-ceb7-f7c4-7862c5527f33@linaro.org> Date: Wed, 11 Jan 2023 23:52:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH 04/13] clk: qcom: cpu-8996: support using GPLL0 as SMUX input Content-Language: en-GB To: Konrad Dybcio , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20230111192004.2509750-1-dmitry.baryshkov@linaro.org> <20230111192004.2509750-5-dmitry.baryshkov@linaro.org> <33a6bf2c-bb93-c183-3915-5b90b72e4503@linaro.org> From: Dmitry Baryshkov In-Reply-To: <33a6bf2c-bb93-c183-3915-5b90b72e4503@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11/01/2023 22:59, Konrad Dybcio wrote: > > > On 11.01.2023 20:19, Dmitry Baryshkov wrote: >> In some cases the driver might need using GPLL0 to drive CPU clocks. >> Bring it in through the sys_apcs_aux clock. >> >> Signed-off-by: Dmitry Baryshkov >> --- > Oh that's new.. downstream doesn't talk about this.. It does, but under the hood of the init procedure. See: /* Select GPLL0 for 300MHz for the perf cluster */ writel_relaxed(0xC, vbases[APC1_BASE] + MUX_OFFSET); > > Konrad >> drivers/clk/qcom/clk-cpu-8996.c | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c >> index d51965fda56d..0e0c00d44c6f 100644 >> --- a/drivers/clk/qcom/clk-cpu-8996.c >> +++ b/drivers/clk/qcom/clk-cpu-8996.c >> @@ -12,6 +12,8 @@ >> * +-------+ >> * XO | | >> * +------------------>0 | >> + * SYS_APCS_AUX | | >> + * +------------------>3 | >> * | | >> * PLL/2 | SMUX +----+ >> * +------->1 | | >> @@ -310,20 +312,29 @@ static const struct clk_ops clk_cpu_8996_pmux_ops = { >> .determine_rate = clk_cpu_8996_pmux_determine_rate, >> }; >> >> +static const struct parent_map smux_parent_map[] = { >> + { .cfg = 0, }, /* xo */ >> + { .cfg = 1, }, /* pll */ >> + { .cfg = 3, }, /* sys_apcs_aux */ >> +}; >> + >> static const struct clk_parent_data pwrcl_smux_parents[] = { >> { .fw_name = "xo" }, >> { .hw = &pwrcl_pll_postdiv.hw }, >> + { .fw_name = "sys_apcs_aux" }, >> }; >> >> static const struct clk_parent_data perfcl_smux_parents[] = { >> { .fw_name = "xo" }, >> { .hw = &perfcl_pll_postdiv.hw }, >> + { .fw_name = "sys_apcs_aux" }, >> }; >> >> static struct clk_regmap_mux pwrcl_smux = { >> .reg = PWRCL_REG_OFFSET + MUX_OFFSET, >> .shift = 2, >> .width = 2, >> + .parent_map = smux_parent_map, >> .clkr.hw.init = &(struct clk_init_data) { >> .name = "pwrcl_smux", >> .parent_data = pwrcl_smux_parents, >> @@ -337,6 +348,7 @@ static struct clk_regmap_mux perfcl_smux = { >> .reg = PERFCL_REG_OFFSET + MUX_OFFSET, >> .shift = 2, >> .width = 2, >> + .parent_map = smux_parent_map, >> .clkr.hw.init = &(struct clk_init_data) { >> .name = "perfcl_smux", >> .parent_data = perfcl_smux_parents, -- With best wishes Dmitry