Re: [net-next,PATCH 2/2] net: stmmac: dwmac-stm32: stm32: add management of stm32mp25 for stm32

[Marek Vasut <marex@denx.de>]

On 6/17/24 1:23 PM, Christophe ROULLIER wrote:

Hi,

>>> +static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data 
>>> *plat_dat)
>>> +{
>>> +    struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
>>> +    u32 reg = dwmac->mode_reg;
>>> +    int val = 0;
>>> +
>>> +    switch (plat_dat->mac_interface) {
>>> +    case PHY_INTERFACE_MODE_MII:
>>> +        break;
>>
>> dwmac->enable_eth_ck does not apply to MII mode ? Why ?
> 
> It is like MP1 and MP13, nothing to set in syscfg register for case MII 
> mode wo crystal.

Have a look at STM32MP15xx RM0436 Figure 83. Peripheral clock 
distribution for Ethernet.

If RCC (top-left corner of the figure) generates 25 MHz MII clock 
(yellow line) on eth_clk_fb (top-right corner), can I set 
ETH_REF_CLK_SEL to position '1' and ETH_SEL[2] to '0' and feed ETH 
(right side) clk_rx_i input with 25 MHz clock that way ?

I seems like this should be possible, at least theoretically. Can you 
check with the hardware/silicon people ?

As a result, the MII/RMII mode would behave in a very similar way, and 
so would GMII/RGMII mode behave in a very similar way. Effectively you 
would end up with this (notice the fallthrough statements):

+	case PHY_INTERFACE_MODE_RMII:
+		val = SYSCFG_ETHCR_ETH_SEL_RMII;
+		fallthrough;
+	case PHY_INTERFACE_MODE_MII:
+		if (dwmac->enable_eth_ck)
+			val |= SYSCFG_ETHCR_ETH_REF_CLK_SEL;
+		break;
+
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		val = SYSCFG_ETHCR_ETH_SEL_RGMII;
+		fallthrough;
+	case PHY_INTERFACE_MODE_GMII:
+		if (dwmac->enable_eth_ck)
+			val |= SYSCFG_ETHCR_ETH_CLK_SEL;
+		break;

[...]