From: Xianwei Zhao <xianwei.zhao@amlogic.com>
To: Kevin Hilman <khilman@baylibre.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>
Subject: Re: [PATCH V2 3/4] soc: c3: Add support for power domains controller
Date: Thu, 27 Jul 2023 10:24:03 +0800 [thread overview]
Message-ID: <39dc0aba-54f7-5c36-01a0-b48d91b6f1c8@amlogic.com> (raw)
In-Reply-To: <7ha5vii9ew.fsf@baylibre.com>
Hi Kevin,
Thanks for your reply.
On 2023/7/27 06:40, Kevin Hilman wrote:
> [ EXTERNAL EMAIL ]
>
> Xianwei Zhao <xianwei.zhao@amlogic.com> writes:
>
>> Add support for C3 Power controller. C3 power control
>> registers are in secure domain, and should be accessed by SMC.
>>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> V1 -> V2: Fixed some formatting.
>> ---
>> drivers/soc/amlogic/meson-secure-pwrc.c | 26 +++++++++++++++++++++++++
>> 1 file changed, 26 insertions(+)
>>
>> diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c b/drivers/soc/amlogic/meson-secure-pwrc.c
>> index c11d65a3e3d9..a1ffebf70de3 100644
>> --- a/drivers/soc/amlogic/meson-secure-pwrc.c
>> +++ b/drivers/soc/amlogic/meson-secure-pwrc.c
>> @@ -11,6 +11,7 @@
>> #include <linux/platform_device.h>
>> #include <linux/pm_domain.h>
>> #include <dt-bindings/power/meson-a1-power.h>
>> +#include <dt-bindings/power/amlogic,c3-pwrc.h>
>> #include <dt-bindings/power/meson-s4-power.h>
>> #include <linux/arm-smccc.h>
>> #include <linux/firmware/meson/meson_sm.h>
>> @@ -120,6 +121,22 @@ static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = {
>> SEC_PD(RSA, 0),
>> };
>>
>> +static struct meson_secure_pwrc_domain_desc c3_pwrc_domains[] = {
>> + SEC_PD(C3_NNA, 0),
>> + SEC_PD(C3_AUDIO, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_SDIOA, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_EMMC, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_USB_COMB, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_SDCARD, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_ETH, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_GE2D, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_CVE, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_GDC_WRAP, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_ISP_TOP, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_MIPI_ISP_WRAP, GENPD_FLAG_ALWAYS_ON),
>> + SEC_PD(C3_VCODEC, 0),
>> +};
>
> All of these domains being hard-coded to ALWAYS_ON looks suspicious, and
> can also be an indicator that the drivers for these domains are not
> (properly) using runtime PM, or not connected to the correct domains the DT.
>
> Similar to the tables for s4 and a1 in this same file, please describe
> the reason that each of these domains needs to be hard coded to be
> always on.
Will do.
>
> Thanks,
>
> Kevin
next prev parent reply other threads:[~2023-07-27 2:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-07 0:37 [PATCH V2 0/4] Power: C3: add power domain driver Xianwei Zhao
2023-07-07 0:37 ` [PATCH V2 1/4] soc: amlogic: use name instead of index as criterion Xianwei Zhao
2023-07-07 7:49 ` Neil Armstrong
2023-07-19 19:44 ` Dmitry Rokosov
2023-07-07 0:37 ` [PATCH V2 2/4] dt-bindings: power: add Amlogic C3 power domains Xianwei Zhao
2023-07-07 15:29 ` Rob Herring
2023-07-07 0:37 ` [PATCH V2 3/4] soc: c3: Add support for power domains controller Xianwei Zhao
2023-07-07 7:50 ` Neil Armstrong
2023-07-26 22:40 ` Kevin Hilman
2023-07-27 2:24 ` Xianwei Zhao [this message]
2023-07-07 0:37 ` [PATCH V2 4/4] arm64: dts: add support for C3 power domain controller Xianwei Zhao
2023-07-07 7:51 ` Neil Armstrong
2023-07-31 9:47 ` (subset) [PATCH V2 0/4] Power: C3: add power domain driver Neil Armstrong
2023-07-31 9:54 ` Neil Armstrong
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