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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abb95cc7451sm436932366b.92.2025.02.18.05.10.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Feb 2025 05:10:21 -0800 (PST) Message-ID: <39efdf43-1f42-4361-85ed-f41df8347471@oss.qualcomm.com> Date: Tue, 18 Feb 2025 14:10:18 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/6] arm64: dts: qcom: sar2130p: add PCIe EP device nodes To: Dmitry Baryshkov , Konrad Dybcio Cc: Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250217-sar2130p-pci-v1-0-94b20ec70a14@linaro.org> <20250217-sar2130p-pci-v1-5-94b20ec70a14@linaro.org> <17aa47df-1daf-4ec2-8f6a-48c3bc375dd3@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: PJvXoZjqUUmul_xHw4n0iF8Zzpx8Six0 X-Proofpoint-GUID: PJvXoZjqUUmul_xHw4n0iF8Zzpx8Six0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-18_05,2025-02-18_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 phishscore=0 mlxlogscore=832 mlxscore=0 bulkscore=0 priorityscore=1501 adultscore=0 impostorscore=0 clxscore=1015 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502180101 On 18.02.2025 4:11 AM, Dmitry Baryshkov wrote: > On Mon, Feb 17, 2025 at 08:23:28PM +0100, Konrad Dybcio wrote: >> On 17.02.2025 7:56 PM, Dmitry Baryshkov wrote: >>> On the Qualcomm AR2 Gen1 platform the second PCIe host can be used >>> either as an RC or as an EP device. Add device node for the PCIe EP. >>> >>> Signed-off-by: Dmitry Baryshkov >>> --- >>> arch/arm64/boot/dts/qcom/sar2130p.dtsi | 53 ++++++++++++++++++++++++++++++++++ >>> 1 file changed, 53 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi >>> index dd832e6816be85817fd1ecc853f8d4c800826bc4..7f007fad6eceebac1b2a863d9f85f2ce3dfb926a 100644 >>> --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi >>> @@ -1474,6 +1474,59 @@ pcie@0 { >>> }; >>> }; >>> >>> + pcie1_ep: pcie-ep@1c08000 { >>> + compatible = "qcom,sar2130p-pcie-ep"; >>> + reg = <0x0 0x01c08000 0x0 0x3000>, >>> + <0x0 0x40000000 0x0 0xf1d>, >>> + <0x0 0x40000f20 0x0 0xa8>, >>> + <0x0 0x40001000 0x0 0x1000>, >>> + <0x0 0x40200000 0x0 0x1000000>, >>> + <0x0 0x01c0b000 0x0 0x1000>, >>> + <0x0 0x40002000 0x0 0x2000>; >>> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", >>> + "mmio", "dma"; >> >> vertical list, please > > Ack > >> >>> + >>> + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, >>> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, >>> + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, >>> + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, >>> + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, >>> + <&gcc GCC_DDRSS_PCIE_SF_CLK>, >>> + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, >>> + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, >>> + <&gcc GCC_QMIP_PCIE_AHB_CLK>; >> >> please make sure this one is actually required > > Hmm, this one seems to be present in pcie0 and pcie1 RC, but in the EP > deivice (in the vendor DT). Are you saying that it is not used for the > EP? I think I just c&p'ed RC clocks here. QMIP clocks did something special. I don't recall what clock ops are translated to, but I suppose keeping them online makes sense.. >> >>> + clock-names = "aux", >>> + "cfg", >>> + "bus_master", >>> + "bus_slave", >>> + "slave_q2a", >>> + "ddrss_sf_tbu", >>> + "aggre_noc_axi", >>> + "cnoc_sf_axi", >>> + "qmip_pcie_ahb"; >>> + >>> + interrupts = , >>> + , >>> + ; >>> + interrupt-names = "global", "doorbell", "dma"; >> >> and here > > This is used for the eDMA implementation. Unlike the vendor kernel, > there is no separate device for eDMA. Sorry, I wrote this before looking at the clocks, I meant please make interrupt-names a vertical list, too Konrad