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Thu, 28 Aug 2025 20:49:56 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D36834004B; Thu, 28 Aug 2025 20:48:10 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E170277A5A4; Thu, 28 Aug 2025 20:46:34 +0200 (CEST) Received: from [10.130.77.120] (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 28 Aug 2025 20:46:33 +0200 Message-ID: <3a0afc93-a7ae-467e-97ad-f1c8d7d7a693@foss.st.com> Date: Thu, 28 Aug 2025 20:46:30 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v13 06/11] PCI: stm32: Add PCIe Endpoint support for STM32MP25 To: Bjorn Helgaas CC: , , , , , , , , , , , , , , , , , , , , , , , , , , References: <20250828171622.GA945192@bhelgaas> From: Christian Bruel Content-Language: en-US In-Reply-To: <20250828171622.GA945192@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-28_04,2025-08-28_01,2025-03-28_01 On 8/28/25 19:16, Bjorn Helgaas wrote: > On Thu, Aug 28, 2025 at 02:12:57PM +0200, Christian Bruel wrote: >> On 8/27/25 20:58, Bjorn Helgaas wrote: >>> On Wed, Aug 20, 2025 at 09:54:06AM +0200, Christian Bruel wrote: >>>> Add driver to configure the STM32MP25 SoC PCIe Gen1 2.5GT/s or Gen2 5GT/s >>>> controller based on the DesignWare PCIe core in endpoint mode. >>> >>>> +static void stm32_pcie_perst_deassert(struct dw_pcie *pci) >>>> +{ >>>> + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); >>>> + struct device *dev = pci->dev; >>>> + struct dw_pcie_ep *ep = &pci->ep; >>>> + int ret; >>>> + >>>> + dev_dbg(dev, "PERST de-asserted by host\n"); >>>> + >>>> + ret = pm_runtime_resume_and_get(dev); >>>> + if (ret < 0) { >>>> + dev_err(dev, "Failed to resume runtime PM: %d\n", ret); >>>> + return; >>>> + } >>>> + >>>> + ret = stm32_pcie_enable_resources(stm32_pcie); >>>> + if (ret) { >>>> + dev_err(dev, "Failed to enable resources: %d\n", ret); >>>> + goto err_pm_put_sync; >>>> + } >>>> + >>>> + /* >>>> + * Need to reprogram the configuration space registers here because the >>>> + * DBI registers were incorrectly reset by the PHY RCC during phy_init(). >>> >>> Is this incorrect reset of DBI registers a software issue or some kind >>> of hardware erratum that might be fixed someday? Or maybe it's just a >>> characteristic of the hardware and thus not really "incorrect"? >>> >>> I do see that qcom_pcie_perst_deassert() in pcie-qcom-ep.c also calls >>> dw_pcie_ep_init_registers() in the qcom_pcie_ep_perst_irq_thread() >>> path. >>> >>> So does pex_ep_event_pex_rst_deassert() (pcie-tegra194.c) in the >>> tegra_pcie_ep_pex_rst_irq() path. >>> >>> But as far as I can tell, none of the other dwc drivers need this, so >>> maybe it's something to do with the glue around the DWC core? >> >> The RCC PHY reset is connected to the Synopsys cold reset logic, which >> explains why the registers need to be restored. This point has been >> addressed in the reference manual. > > OK. I dropped "incorrectly" from the comment because I think future > readers will wonder about whether or how this could be fixed, and it > sounds like it's just a feature of the hardware that we need to deal > with. OK, thank you. "unexpectedly" would have been appropriate, but just drop it is even better. > >>>> + */ >>>> + ret = dw_pcie_ep_init_registers(ep); >>>> + if (ret) { >>>> + dev_err(dev, "Failed to complete initialization: %d\n", ret); >>>> + goto err_disable_resources; >>>> + } >>