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([2a02:810d:15c0:828:5310:35c7:6f9e:2cd3]) by smtp.gmail.com with ESMTPSA id y26-20020a170906071a00b008b2714f4d8asm5646123ejb.181.2023.03.06.23.47.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Mar 2023 23:47:13 -0800 (PST) Message-ID: <3a27febc-4d4e-1cfd-45dc-6ade4f25ca13@linaro.org> Date: Tue, 7 Mar 2023 08:47:11 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v2 0/6] clk: samsung: exynos850: Add missing clocks for PM Content-Language: en-US To: Sam Protsenko Cc: Chanwoo Choi , Sylwester Nawrocki , Rob Herring , Chanho Park , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tomasz Figa , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Alim Akhtar , linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org, Michael Turquette , David Virag , Sumit Semwal References: <20230223042133.26551-1-semen.protsenko@linaro.org> <167811290503.11716.15730246749418548221.b4-ty@linaro.org> <48c8a0cf-08dc-a831-33ef-3b8e32eef2d3@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 06/03/2023 19:55, Sam Protsenko wrote: > On Mon, 6 Mar 2023 at 09:51, Krzysztof Kozlowski > wrote: >> >> On 06/03/2023 15:28, Krzysztof Kozlowski wrote: >>> On Wed, 22 Feb 2023 22:21:27 -0600, Sam Protsenko wrote: >>>> As a part of preparation for PM enablement in Exynos850 clock driver, >>>> this patch series implements CMU_G3D, and also main gate clocks for AUD >>>> and HSI CMUs. The series brings corresponding changes to bindings, the >>>> driver and SoC dts file. >>>> >>>> Changes in v2: >>>> - Rebased all patches on top of the most recent soc/for-next tree >>>> - Added A-b and R-b tags >>>> - Minor fixes >>>> >>>> [...] >>> >>> Applied, thanks! >>> >>> [1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D >>> https://git.kernel.org/krzk/linux/c/067ba1605806e52118bb598afb357718df9f0e19 >>> [2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks >>> https://git.kernel.org/krzk/linux/c/e289665ed0d6df9fca3ebc128f1232d305e4600b >>> [3/6] clk: samsung: clk-pll: Implement pll0818x PLL type >>> https://git.kernel.org/krzk/linux/c/a6feedab8ab9a9e4483deb0bcc87919d92c88b7e >>> [4/6] clk: samsung: exynos850: Implement CMU_G3D domain >>> https://git.kernel.org/krzk/linux/c/c5704a56893b4e77e434597c7c53d878bb3073b0 >>> [5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks >>> https://git.kernel.org/krzk/linux/c/d8d12e0d079aff4b1d8079a0a55944c0596f1d67 >>> [6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC >>> https://git.kernel.org/krzk/linux/c/ad8f6ad9a4f219950df65731a8ff91baa022c4b0 >> >> And builds are broken. Please mention in cover letter or commit >> dependencies and ordering... >> > > Just checked all most recent commits on your for-next and next/clk > branches. Seem to build fine for me. AFAIR I checked all patches in > that series, and I guess there shouldn't be any issues if you apply > those in the same order they are numbered inside the series. Or you > mean you have some clash between different series? Anyways, I'm glad > to help, but I'd need more details on where exactly the problem is (or > maybe you already fixed it?). The builds were failing after I applied everything to respective branches (so DTS separate). I did not notice that your DTS and driver (both) depend on bindings header constant. This requires special handling. It actually always required, because it was going through different trees. Now it goes through my tree, but I still need to handle it. I reworked the branches and force-pushed, thus you did not see the exact issue. Best regards, Krzysztof