[PATCH v2 0/5] sdhci-brcmstb SD host controller SoC specific enhancements

[PATCH v2 0/5] sdhci-brcmstb SD host controller SoC specific enhancements

[Kamal Dasu]

sdhci-brcmstb HS200 configuration for BCM72116 and PM register save restore
changes applicable to various SoCs. 

v2 changes:
 - Separate commit for SDIO_CFG register defines that moved
 - Implemented cosmetic changes proposed for initial change for :
     "mmc: sdhci-brcmstb: clear CFG_OP_DLY when using HS200"
 - Moved BCM74371 support in a separate commit    
 - Implemented review comments and reorganized code for :
     "mmc: sdhci-brcmstb: save and restore registers during PM"
 - Added Reviewed-by and Acked-by tags wherever applicable 

Kamal Dasu (5):
  dt-bindings: mmc: Add support for BCM72116 and BCM74371 SD host
    controller
  mmc: sdhci-brcmstb: move SDIO_CFG_CQ_CAPABILITY define
  mmc: sdhci-brcmstb: clear CFG_OP_DLY when using HS200
  mmc: sdhci-brcmstb: Add BCM74371 support
  mmc: sdhci-brcmstb: save and restore registers during PM

 .../bindings/mmc/brcm,sdhci-brcmstb.yaml      |   2 +
 drivers/mmc/host/sdhci-brcmstb.c              | 154 +++++++++++++++++-
 2 files changed, 147 insertions(+), 9 deletions(-)

-- 
2.34.1

[PATCH v2 1/5] dt-bindings: mmc: Add support for BCM72116 and BCM74371 SD host controller

[Kamal Dasu]

Updating compatibility to support BCM72116 and BCM74371 SD host controller
similar to other settop SoCs.

Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
index eee6be7a7867..720d0762078f 100644
--- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
+++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
@@ -21,9 +21,11 @@ properties:
       - items:
           - enum:
               - brcm,bcm2712-sdhci
+              - brcm,bcm72116-sdhci
               - brcm,bcm74165b0-sdhci
               - brcm,bcm7445-sdhci
               - brcm,bcm7425-sdhci
+              - brcm,bcm74371-sdhci
           - const: brcm,sdhci-brcmstb
 
   reg:
-- 
2.34.1

[PATCH v2 2/5] mmc: sdhci-brcmstb: move SDIO_CFG_CQ_CAPABILITY define

[Kamal Dasu]

Moving SDIO_CFG_CQ_CAPABILITY register defines to be in sorted order for
better readability.

Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
---
 drivers/mmc/host/sdhci-brcmstb.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
index efc2f3bdc631..f81cc1889ac9 100644
--- a/drivers/mmc/host/sdhci-brcmstb.c
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -31,13 +31,11 @@
 
 #define SDHCI_ARASAN_CQE_BASE_ADDR		0x200
 
-#define SDIO_CFG_CQ_CAPABILITY			0x4c
-#define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
-
 #define SDIO_CFG_CTRL				0x0
 #define SDIO_CFG_CTRL_SDCD_N_TEST_EN		BIT(31)
 #define SDIO_CFG_CTRL_SDCD_N_TEST_LEV		BIT(30)
-
+#define SDIO_CFG_CQ_CAPABILITY			0x4c
+#define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
 #define SDIO_CFG_MAX_50MHZ_MODE			0x1ac
 #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE	BIT(31)
 #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE		BIT(0)
-- 
2.34.1

[PATCH v2 3/5] mmc: sdhci-brcmstb: clear CFG_OP_DLY when using HS200

[Kamal Dasu]

Clear SDIO_1_CFG_OP_DLY register when using HS200 mode to be
compliant with timing spec.  We only need this for on BCM72116
SoCs.

Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
 drivers/mmc/host/sdhci-brcmstb.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
index f81cc1889ac9..d25bf71d79f4 100644
--- a/drivers/mmc/host/sdhci-brcmstb.c
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -34,6 +34,8 @@
 #define SDIO_CFG_CTRL				0x0
 #define SDIO_CFG_CTRL_SDCD_N_TEST_EN		BIT(31)
 #define SDIO_CFG_CTRL_SDCD_N_TEST_LEV		BIT(30)
+#define SDIO_CFG_OP_DLY				0x34
+#define SDIO_CFG_OP_DLY_DEFAULT			0x80000003
 #define SDIO_CFG_CQ_CAPABILITY			0x4c
 #define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
 #define SDIO_CFG_MAX_50MHZ_MODE			0x1ac
@@ -210,6 +212,21 @@ static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host)
 	}
 }
 
+static void sdhci_brcmstb_set_72116_uhs_signaling(struct sdhci_host *host, unsigned int timing)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	u32 reg;
+
+	/* no change to SDIO_CFG_OP_DLY_DEFAULT when using preset clk rate */
+	if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
+		return;
+
+	reg = (timing == MMC_TIMING_MMC_HS200) ? 0 : SDIO_CFG_OP_DLY_DEFAULT;
+	writel(reg, priv->cfg_regs + SDIO_CFG_OP_DLY);
+	sdhci_set_uhs_signaling(host, timing);
+}
+
 static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)
 {
 	sdhci_dumpregs(mmc_priv(mmc));
@@ -250,6 +267,13 @@ static struct sdhci_ops sdhci_brcmstb_ops_2712 = {
 	.set_uhs_signaling = sdhci_set_uhs_signaling,
 };
 
+static struct sdhci_ops sdhci_brcmstb_ops_72116 = {
+	.set_clock = sdhci_set_clock,
+	.set_bus_width = sdhci_set_bus_width,
+	.reset = sdhci_reset,
+	.set_uhs_signaling = sdhci_brcmstb_set_72116_uhs_signaling,
+};
+
 static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
 	.set_clock = sdhci_brcmstb_set_clock,
 	.set_bus_width = sdhci_set_bus_width,
@@ -280,6 +304,11 @@ static struct brcmstb_match_priv match_priv_7445 = {
 	.ops = &sdhci_brcmstb_ops,
 };
 
+static struct brcmstb_match_priv match_priv_72116 = {
+	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
+	.ops = &sdhci_brcmstb_ops_72116,
+};
+
 static const struct brcmstb_match_priv match_priv_7216 = {
 	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
 	.hs400es = sdhci_brcmstb_hs400es,
@@ -296,6 +325,7 @@ static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = {
 	{ .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 },
 	{ .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
 	{ .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
+	{ .compatible = "brcm,bcm72116-sdhci", .data = &match_priv_72116 },
 	{ .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
 	{ .compatible = "brcm,bcm74165b0-sdhci", .data = &match_priv_74165b0 },
 	{},
-- 
2.34.1

[PATCH v2 4/5] mmc: sdhci-brcmstb: Add BCM74371 support

[Kamal Dasu]

Added "brcm,bcm74371-sdhci" compatibility to the controller driver.

Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
---
 drivers/mmc/host/sdhci-brcmstb.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
index d25bf71d79f4..42709ca8111d 100644
--- a/drivers/mmc/host/sdhci-brcmstb.c
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -299,6 +299,11 @@ static struct brcmstb_match_priv match_priv_7425 = {
 	.ops = &sdhci_brcmstb_ops,
 };
 
+static struct brcmstb_match_priv match_priv_74371 = {
+	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
+	.ops = &sdhci_brcmstb_ops,
+};
+
 static struct brcmstb_match_priv match_priv_7445 = {
 	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
 	.ops = &sdhci_brcmstb_ops,
@@ -324,6 +329,7 @@ static struct brcmstb_match_priv match_priv_74165b0 = {
 static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = {
 	{ .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 },
 	{ .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
+	{ .compatible = "brcm,bcm74371-sdhci", .data = &match_priv_74371 },
 	{ .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
 	{ .compatible = "brcm,bcm72116-sdhci", .data = &match_priv_72116 },
 	{ .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
-- 
2.34.1

[PATCH v2 5/5] mmc: brcmstb: save and restore registers during PM

[Kamal Dasu]

Added support to save and restore registers that are critical
during PM.

Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
---
 drivers/mmc/host/sdhci-brcmstb.c | 112 +++++++++++++++++++++++++++++--
 1 file changed, 107 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
index 42709ca8111d..7de395c86f2f 100644
--- a/drivers/mmc/host/sdhci-brcmstb.c
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -38,28 +38,109 @@
 #define SDIO_CFG_OP_DLY_DEFAULT			0x80000003
 #define SDIO_CFG_CQ_CAPABILITY			0x4c
 #define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
+#define SDIO_CFG_SD_PIN_SEL			0x44
+#define SDIO_CFG_V1_SD_PIN_SEL			0x54
+#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL		0x7C
 #define SDIO_CFG_MAX_50MHZ_MODE			0x1ac
 #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE	BIT(31)
 #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE		BIT(0)
 
+#define SDIO_BOOT_MAIN_CTL			0x0
+
 #define MMC_CAP_HSE_MASK	(MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V)
 /* Select all SD UHS type I SDR speed above 50MB/s */
 #define MMC_CAP_UHS_I_SDR_MASK	(MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)
 
-struct sdhci_brcmstb_priv {
-	void __iomem *cfg_regs;
-	unsigned int flags;
-	struct clk *base_clk;
-	u32 base_freq_hz;
+enum cfg_core_ver {
+	SDIO_CFG_CORE_V1 = 1,
+	SDIO_CFG_CORE_V2,
+};
+
+struct sdhci_brcmstb_saved_regs {
+	u32 sd_pin_sel;
+	u32 phy_sw_mode0_rxctrl;
+	u32 max_50mhz_mode;
+	u32 boot_main_ctl;
 };
 
 struct brcmstb_match_priv {
 	void (*cfginit)(struct sdhci_host *host);
 	void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
+	void (*save_restore_regs)(struct mmc_host *mmc, int save);
 	struct sdhci_ops *ops;
 	const unsigned int flags;
 };
 
+struct sdhci_brcmstb_priv {
+	void __iomem *cfg_regs;
+	void __iomem *boot_regs;
+	struct sdhci_brcmstb_saved_regs saved_regs;
+	unsigned int flags;
+	struct clk *base_clk;
+	u32 base_freq_hz;
+	const struct brcmstb_match_priv *match_priv;
+};
+
+static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
+	void __iomem *cr = priv->cfg_regs;
+	bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
+
+	if (is_emmc && priv->boot_regs)
+		sr->boot_main_ctl = readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL);
+
+	if (ver == SDIO_CFG_CORE_V1) {
+		sr->sd_pin_sel = readl(cr + SDIO_CFG_V1_SD_PIN_SEL);
+		return;
+	}
+
+	sr->sd_pin_sel = readl(cr + SDIO_CFG_SD_PIN_SEL);
+	sr->phy_sw_mode0_rxctrl = readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
+	sr->max_50mhz_mode = readl(cr + SDIO_CFG_MAX_50MHZ_MODE);
+}
+
+static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
+	void __iomem *cr = priv->cfg_regs;
+	bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
+
+	if (is_emmc && priv->boot_regs)
+		writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL);
+
+	if (ver == SDIO_CFG_CORE_V1) {
+		writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
+		return;
+	}
+
+	writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
+	writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
+	writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE);
+}
+
+static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int save)
+{
+	if (save)
+		sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1);
+	else
+		sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1);
+}
+
+static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int save)
+{
+	if (save)
+		sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2);
+	else
+		sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2);
+}
+
 static inline void enable_clock_gating(struct sdhci_host *host)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -306,22 +387,26 @@ static struct brcmstb_match_priv match_priv_74371 = {
 
 static struct brcmstb_match_priv match_priv_7445 = {
 	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
+	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
 	.ops = &sdhci_brcmstb_ops,
 };
 
 static struct brcmstb_match_priv match_priv_72116 = {
 	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
+	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
 	.ops = &sdhci_brcmstb_ops_72116,
 };
 
 static const struct brcmstb_match_priv match_priv_7216 = {
 	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
+	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
 	.hs400es = sdhci_brcmstb_hs400es,
 	.ops = &sdhci_brcmstb_ops_7216,
 };
 
 static struct brcmstb_match_priv match_priv_74165b0 = {
 	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
+	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
 	.hs400es = sdhci_brcmstb_hs400es,
 	.ops = &sdhci_brcmstb_ops_74165b0,
 };
@@ -429,6 +514,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
 
 	pltfm_host = sdhci_priv(host);
 	priv = sdhci_pltfm_priv(pltfm_host);
+	priv->match_priv = match->data;
 	if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
 		priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
 		match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
@@ -446,6 +532,13 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
 	if (res)
 		goto err;
 
+	/* map non-standard BOOT registers if present */
+	if (host->mmc->caps & MMC_CAP_NONREMOVABLE) {
+		priv->boot_regs = devm_platform_get_and_ioremap_resource(pdev, 2, NULL);
+		if (IS_ERR(priv->boot_regs))
+			priv->boot_regs = NULL;
+	}
+
 	/*
 	 * Automatic clock gating does not work for SD cards that may
 	 * voltage switch so only enable it for non-removable devices.
@@ -536,8 +629,13 @@ static int sdhci_brcmstb_suspend(struct device *dev)
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	const struct brcmstb_match_priv *match_priv = priv->match_priv;
+
 	int ret;
 
+	if (match_priv->save_restore_regs)
+		match_priv->save_restore_regs(host->mmc, 1);
+
 	clk_disable_unprepare(priv->base_clk);
 	if (host->mmc->caps2 & MMC_CAP2_CQE) {
 		ret = cqhci_suspend(host->mmc);
@@ -553,6 +651,7 @@ static int sdhci_brcmstb_resume(struct device *dev)
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	const struct brcmstb_match_priv *match_priv = priv->match_priv;
 	int ret;
 
 	ret = sdhci_pltfm_resume(dev);
@@ -569,6 +668,9 @@ static int sdhci_brcmstb_resume(struct device *dev)
 			ret = clk_set_rate(priv->base_clk, priv->base_freq_hz);
 	}
 
+	if (match_priv->save_restore_regs)
+		match_priv->save_restore_regs(host->mmc, 0);
+
 	if (host->mmc->caps2 & MMC_CAP2_CQE)
 		ret = cqhci_resume(host->mmc);
 
-- 
2.34.1

[PATCH v2 5/5] mmc: sdhci-brcmstb: save and restore registers during PM

[Kamal Dasu]

Added support to save and restore registers that are critical
during PM.

Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
---
 drivers/mmc/host/sdhci-brcmstb.c | 112 +++++++++++++++++++++++++++++--
 1 file changed, 107 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
index 42709ca8111d..7de395c86f2f 100644
--- a/drivers/mmc/host/sdhci-brcmstb.c
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -38,28 +38,109 @@
 #define SDIO_CFG_OP_DLY_DEFAULT			0x80000003
 #define SDIO_CFG_CQ_CAPABILITY			0x4c
 #define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
+#define SDIO_CFG_SD_PIN_SEL			0x44
+#define SDIO_CFG_V1_SD_PIN_SEL			0x54
+#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL		0x7C
 #define SDIO_CFG_MAX_50MHZ_MODE			0x1ac
 #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE	BIT(31)
 #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE		BIT(0)
 
+#define SDIO_BOOT_MAIN_CTL			0x0
+
 #define MMC_CAP_HSE_MASK	(MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V)
 /* Select all SD UHS type I SDR speed above 50MB/s */
 #define MMC_CAP_UHS_I_SDR_MASK	(MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)
 
-struct sdhci_brcmstb_priv {
-	void __iomem *cfg_regs;
-	unsigned int flags;
-	struct clk *base_clk;
-	u32 base_freq_hz;
+enum cfg_core_ver {
+	SDIO_CFG_CORE_V1 = 1,
+	SDIO_CFG_CORE_V2,
+};
+
+struct sdhci_brcmstb_saved_regs {
+	u32 sd_pin_sel;
+	u32 phy_sw_mode0_rxctrl;
+	u32 max_50mhz_mode;
+	u32 boot_main_ctl;
 };
 
 struct brcmstb_match_priv {
 	void (*cfginit)(struct sdhci_host *host);
 	void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
+	void (*save_restore_regs)(struct mmc_host *mmc, int save);
 	struct sdhci_ops *ops;
 	const unsigned int flags;
 };
 
+struct sdhci_brcmstb_priv {
+	void __iomem *cfg_regs;
+	void __iomem *boot_regs;
+	struct sdhci_brcmstb_saved_regs saved_regs;
+	unsigned int flags;
+	struct clk *base_clk;
+	u32 base_freq_hz;
+	const struct brcmstb_match_priv *match_priv;
+};
+
+static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
+	void __iomem *cr = priv->cfg_regs;
+	bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
+
+	if (is_emmc && priv->boot_regs)
+		sr->boot_main_ctl = readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL);
+
+	if (ver == SDIO_CFG_CORE_V1) {
+		sr->sd_pin_sel = readl(cr + SDIO_CFG_V1_SD_PIN_SEL);
+		return;
+	}
+
+	sr->sd_pin_sel = readl(cr + SDIO_CFG_SD_PIN_SEL);
+	sr->phy_sw_mode0_rxctrl = readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
+	sr->max_50mhz_mode = readl(cr + SDIO_CFG_MAX_50MHZ_MODE);
+}
+
+static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
+	void __iomem *cr = priv->cfg_regs;
+	bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
+
+	if (is_emmc && priv->boot_regs)
+		writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL);
+
+	if (ver == SDIO_CFG_CORE_V1) {
+		writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
+		return;
+	}
+
+	writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
+	writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
+	writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE);
+}
+
+static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int save)
+{
+	if (save)
+		sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1);
+	else
+		sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1);
+}
+
+static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int save)
+{
+	if (save)
+		sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2);
+	else
+		sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2);
+}
+
 static inline void enable_clock_gating(struct sdhci_host *host)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -306,22 +387,26 @@ static struct brcmstb_match_priv match_priv_74371 = {
 
 static struct brcmstb_match_priv match_priv_7445 = {
 	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
+	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
 	.ops = &sdhci_brcmstb_ops,
 };
 
 static struct brcmstb_match_priv match_priv_72116 = {
 	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
+	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
 	.ops = &sdhci_brcmstb_ops_72116,
 };
 
 static const struct brcmstb_match_priv match_priv_7216 = {
 	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
+	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
 	.hs400es = sdhci_brcmstb_hs400es,
 	.ops = &sdhci_brcmstb_ops_7216,
 };
 
 static struct brcmstb_match_priv match_priv_74165b0 = {
 	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
+	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
 	.hs400es = sdhci_brcmstb_hs400es,
 	.ops = &sdhci_brcmstb_ops_74165b0,
 };
@@ -429,6 +514,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
 
 	pltfm_host = sdhci_priv(host);
 	priv = sdhci_pltfm_priv(pltfm_host);
+	priv->match_priv = match->data;
 	if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
 		priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
 		match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
@@ -446,6 +532,13 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
 	if (res)
 		goto err;
 
+	/* map non-standard BOOT registers if present */
+	if (host->mmc->caps & MMC_CAP_NONREMOVABLE) {
+		priv->boot_regs = devm_platform_get_and_ioremap_resource(pdev, 2, NULL);
+		if (IS_ERR(priv->boot_regs))
+			priv->boot_regs = NULL;
+	}
+
 	/*
 	 * Automatic clock gating does not work for SD cards that may
 	 * voltage switch so only enable it for non-removable devices.
@@ -536,8 +629,13 @@ static int sdhci_brcmstb_suspend(struct device *dev)
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	const struct brcmstb_match_priv *match_priv = priv->match_priv;
+
 	int ret;
 
+	if (match_priv->save_restore_regs)
+		match_priv->save_restore_regs(host->mmc, 1);
+
 	clk_disable_unprepare(priv->base_clk);
 	if (host->mmc->caps2 & MMC_CAP2_CQE) {
 		ret = cqhci_suspend(host->mmc);
@@ -553,6 +651,7 @@ static int sdhci_brcmstb_resume(struct device *dev)
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	const struct brcmstb_match_priv *match_priv = priv->match_priv;
 	int ret;
 
 	ret = sdhci_pltfm_resume(dev);
@@ -569,6 +668,9 @@ static int sdhci_brcmstb_resume(struct device *dev)
 			ret = clk_set_rate(priv->base_clk, priv->base_freq_hz);
 	}
 
+	if (match_priv->save_restore_regs)
+		match_priv->save_restore_regs(host->mmc, 0);
+
 	if (host->mmc->caps2 & MMC_CAP2_CQE)
 		ret = cqhci_resume(host->mmc);
 
-- 
2.34.1

Re: [PATCH v2 5/5] mmc: brcmstb: save and restore registers during PM

[Kamal Dasu]

[-- Attachment #1: Type: text/plain, Size: 8926 bytes --]

On Tue, Oct 7, 2025 at 10:05 AM Kamal Dasu <kamal.dasu@broadcom.com> wrote:
>

Ignore this patch  as I changed the subject and sent a different v 5/5
with the right subject:
" [PATCH v2 5/5] mmc: sdhci-brcmstb: save and restore registers during PM"



> Added support to save and restore registers that are critical
> during PM.
>
> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
> ---
>  drivers/mmc/host/sdhci-brcmstb.c | 112 +++++++++++++++++++++++++++++--
>  1 file changed, 107 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
> index 42709ca8111d..7de395c86f2f 100644
> --- a/drivers/mmc/host/sdhci-brcmstb.c
> +++ b/drivers/mmc/host/sdhci-brcmstb.c
> @@ -38,28 +38,109 @@
>  #define SDIO_CFG_OP_DLY_DEFAULT                        0x80000003
>  #define SDIO_CFG_CQ_CAPABILITY                 0x4c
>  #define SDIO_CFG_CQ_CAPABILITY_FMUL            GENMASK(13, 12)
> +#define SDIO_CFG_SD_PIN_SEL                    0x44
> +#define SDIO_CFG_V1_SD_PIN_SEL                 0x54
> +#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL         0x7C
>  #define SDIO_CFG_MAX_50MHZ_MODE                        0x1ac
>  #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31)
>  #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE         BIT(0)
>
> +#define SDIO_BOOT_MAIN_CTL                     0x0
> +
>  #define MMC_CAP_HSE_MASK       (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V)
>  /* Select all SD UHS type I SDR speed above 50MB/s */
>  #define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)
>
> -struct sdhci_brcmstb_priv {
> -       void __iomem *cfg_regs;
> -       unsigned int flags;
> -       struct clk *base_clk;
> -       u32 base_freq_hz;
> +enum cfg_core_ver {
> +       SDIO_CFG_CORE_V1 = 1,
> +       SDIO_CFG_CORE_V2,
> +};
> +
> +struct sdhci_brcmstb_saved_regs {
> +       u32 sd_pin_sel;
> +       u32 phy_sw_mode0_rxctrl;
> +       u32 max_50mhz_mode;
> +       u32 boot_main_ctl;
>  };
>
>  struct brcmstb_match_priv {
>         void (*cfginit)(struct sdhci_host *host);
>         void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
> +       void (*save_restore_regs)(struct mmc_host *mmc, int save);
>         struct sdhci_ops *ops;
>         const unsigned int flags;
>  };
>
> +struct sdhci_brcmstb_priv {
> +       void __iomem *cfg_regs;
> +       void __iomem *boot_regs;
> +       struct sdhci_brcmstb_saved_regs saved_regs;
> +       unsigned int flags;
> +       struct clk *base_clk;
> +       u32 base_freq_hz;
> +       const struct brcmstb_match_priv *match_priv;
> +};
> +
> +static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
> +{
> +       struct sdhci_host *host = mmc_priv(mmc);
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +       struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
> +       void __iomem *cr = priv->cfg_regs;
> +       bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
> +
> +       if (is_emmc && priv->boot_regs)
> +               sr->boot_main_ctl = readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL);
> +
> +       if (ver == SDIO_CFG_CORE_V1) {
> +               sr->sd_pin_sel = readl(cr + SDIO_CFG_V1_SD_PIN_SEL);
> +               return;
> +       }
> +
> +       sr->sd_pin_sel = readl(cr + SDIO_CFG_SD_PIN_SEL);
> +       sr->phy_sw_mode0_rxctrl = readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
> +       sr->max_50mhz_mode = readl(cr + SDIO_CFG_MAX_50MHZ_MODE);
> +}
> +
> +static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
> +{
> +       struct sdhci_host *host = mmc_priv(mmc);
> +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +       struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +       struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
> +       void __iomem *cr = priv->cfg_regs;
> +       bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
> +
> +       if (is_emmc && priv->boot_regs)
> +               writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL);
> +
> +       if (ver == SDIO_CFG_CORE_V1) {
> +               writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
> +               return;
> +       }
> +
> +       writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
> +       writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
> +       writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE);
> +}
> +
> +static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int save)
> +{
> +       if (save)
> +               sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1);
> +       else
> +               sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1);
> +}
> +
> +static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int save)
> +{
> +       if (save)
> +               sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2);
> +       else
> +               sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2);
> +}
> +
>  static inline void enable_clock_gating(struct sdhci_host *host)
>  {
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> @@ -306,22 +387,26 @@ static struct brcmstb_match_priv match_priv_74371 = {
>
>  static struct brcmstb_match_priv match_priv_7445 = {
>         .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
> +       .save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
>         .ops = &sdhci_brcmstb_ops,
>  };
>
>  static struct brcmstb_match_priv match_priv_72116 = {
>         .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
> +       .save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
>         .ops = &sdhci_brcmstb_ops_72116,
>  };
>
>  static const struct brcmstb_match_priv match_priv_7216 = {
>         .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
> +       .save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
>         .hs400es = sdhci_brcmstb_hs400es,
>         .ops = &sdhci_brcmstb_ops_7216,
>  };
>
>  static struct brcmstb_match_priv match_priv_74165b0 = {
>         .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
> +       .save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
>         .hs400es = sdhci_brcmstb_hs400es,
>         .ops = &sdhci_brcmstb_ops_74165b0,
>  };
> @@ -429,6 +514,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
>
>         pltfm_host = sdhci_priv(host);
>         priv = sdhci_pltfm_priv(pltfm_host);
> +       priv->match_priv = match->data;
>         if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
>                 priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
>                 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
> @@ -446,6 +532,13 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
>         if (res)
>                 goto err;
>
> +       /* map non-standard BOOT registers if present */
> +       if (host->mmc->caps & MMC_CAP_NONREMOVABLE) {
> +               priv->boot_regs = devm_platform_get_and_ioremap_resource(pdev, 2, NULL);
> +               if (IS_ERR(priv->boot_regs))
> +                       priv->boot_regs = NULL;
> +       }
> +
>         /*
>          * Automatic clock gating does not work for SD cards that may
>          * voltage switch so only enable it for non-removable devices.
> @@ -536,8 +629,13 @@ static int sdhci_brcmstb_suspend(struct device *dev)
>         struct sdhci_host *host = dev_get_drvdata(dev);
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>         struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +       const struct brcmstb_match_priv *match_priv = priv->match_priv;
> +
>         int ret;
>
> +       if (match_priv->save_restore_regs)
> +               match_priv->save_restore_regs(host->mmc, 1);
> +
>         clk_disable_unprepare(priv->base_clk);
>         if (host->mmc->caps2 & MMC_CAP2_CQE) {
>                 ret = cqhci_suspend(host->mmc);
> @@ -553,6 +651,7 @@ static int sdhci_brcmstb_resume(struct device *dev)
>         struct sdhci_host *host = dev_get_drvdata(dev);
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>         struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +       const struct brcmstb_match_priv *match_priv = priv->match_priv;
>         int ret;
>
>         ret = sdhci_pltfm_resume(dev);
> @@ -569,6 +668,9 @@ static int sdhci_brcmstb_resume(struct device *dev)
>                         ret = clk_set_rate(priv->base_clk, priv->base_freq_hz);
>         }
>
> +       if (match_priv->save_restore_regs)
> +               match_priv->save_restore_regs(host->mmc, 0);
> +
>         if (host->mmc->caps2 & MMC_CAP2_CQE)
>                 ret = cqhci_resume(host->mmc);
>
> --
> 2.34.1
>

[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 5461 bytes --]

Re: [PATCH v2 2/5] mmc: sdhci-brcmstb: move SDIO_CFG_CQ_CAPABILITY define

[Adrian Hunter]

On 07/10/2025 17:04, Kamal Dasu wrote:
> Moving SDIO_CFG_CQ_CAPABILITY register defines to be in sorted order for
> better readability.
> 
> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-brcmstb.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
> index efc2f3bdc631..f81cc1889ac9 100644
> --- a/drivers/mmc/host/sdhci-brcmstb.c
> +++ b/drivers/mmc/host/sdhci-brcmstb.c
> @@ -31,13 +31,11 @@
>  
>  #define SDHCI_ARASAN_CQE_BASE_ADDR		0x200
>  
> -#define SDIO_CFG_CQ_CAPABILITY			0x4c
> -#define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
> -
>  #define SDIO_CFG_CTRL				0x0
>  #define SDIO_CFG_CTRL_SDCD_N_TEST_EN		BIT(31)
>  #define SDIO_CFG_CTRL_SDCD_N_TEST_LEV		BIT(30)
> -
> +#define SDIO_CFG_CQ_CAPABILITY			0x4c
> +#define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
>  #define SDIO_CFG_MAX_50MHZ_MODE			0x1ac
>  #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE	BIT(31)
>  #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE		BIT(0)

Re: [PATCH v2 4/5] mmc: sdhci-brcmstb: Add BCM74371 support

[Adrian Hunter]

On 07/10/2025 17:04, Kamal Dasu wrote:
> Added "brcm,bcm74371-sdhci" compatibility to the controller driver.
> 
> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-brcmstb.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
> index d25bf71d79f4..42709ca8111d 100644
> --- a/drivers/mmc/host/sdhci-brcmstb.c
> +++ b/drivers/mmc/host/sdhci-brcmstb.c
> @@ -299,6 +299,11 @@ static struct brcmstb_match_priv match_priv_7425 = {
>  	.ops = &sdhci_brcmstb_ops,
>  };
>  
> +static struct brcmstb_match_priv match_priv_74371 = {
> +	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
> +	.ops = &sdhci_brcmstb_ops,
> +};
> +
>  static struct brcmstb_match_priv match_priv_7445 = {
>  	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
>  	.ops = &sdhci_brcmstb_ops,
> @@ -324,6 +329,7 @@ static struct brcmstb_match_priv match_priv_74165b0 = {
>  static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = {
>  	{ .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 },
>  	{ .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
> +	{ .compatible = "brcm,bcm74371-sdhci", .data = &match_priv_74371 },
>  	{ .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
>  	{ .compatible = "brcm,bcm72116-sdhci", .data = &match_priv_72116 },
>  	{ .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },

Re: [PATCH v2 5/5] mmc: brcmstb: save and restore registers during PM

[Adrian Hunter]

On 07/10/2025 17:04, Kamal Dasu wrote:
> Added support to save and restore registers that are critical
> during PM.
> 
> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
> ---
>  drivers/mmc/host/sdhci-brcmstb.c | 112 +++++++++++++++++++++++++++++--
>  1 file changed, 107 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
> index 42709ca8111d..7de395c86f2f 100644
> --- a/drivers/mmc/host/sdhci-brcmstb.c
> +++ b/drivers/mmc/host/sdhci-brcmstb.c
> @@ -38,28 +38,109 @@
>  #define SDIO_CFG_OP_DLY_DEFAULT			0x80000003
>  #define SDIO_CFG_CQ_CAPABILITY			0x4c
>  #define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
> +#define SDIO_CFG_SD_PIN_SEL			0x44
> +#define SDIO_CFG_V1_SD_PIN_SEL			0x54
> +#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL		0x7C
>  #define SDIO_CFG_MAX_50MHZ_MODE			0x1ac
>  #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE	BIT(31)
>  #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE		BIT(0)
>  
> +#define SDIO_BOOT_MAIN_CTL			0x0
> +
>  #define MMC_CAP_HSE_MASK	(MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V)
>  /* Select all SD UHS type I SDR speed above 50MB/s */
>  #define MMC_CAP_UHS_I_SDR_MASK	(MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)
>  
> -struct sdhci_brcmstb_priv {
> -	void __iomem *cfg_regs;
> -	unsigned int flags;
> -	struct clk *base_clk;
> -	u32 base_freq_hz;
> +enum cfg_core_ver {
> +	SDIO_CFG_CORE_V1 = 1,
> +	SDIO_CFG_CORE_V2,
> +};
> +
> +struct sdhci_brcmstb_saved_regs {
> +	u32 sd_pin_sel;
> +	u32 phy_sw_mode0_rxctrl;
> +	u32 max_50mhz_mode;
> +	u32 boot_main_ctl;
>  };
>  
>  struct brcmstb_match_priv {
>  	void (*cfginit)(struct sdhci_host *host);
>  	void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
> +	void (*save_restore_regs)(struct mmc_host *mmc, int save);
>  	struct sdhci_ops *ops;
>  	const unsigned int flags;
>  };
>  
> +struct sdhci_brcmstb_priv {
> +	void __iomem *cfg_regs;
> +	void __iomem *boot_regs;
> +	struct sdhci_brcmstb_saved_regs saved_regs;
> +	unsigned int flags;
> +	struct clk *base_clk;
> +	u32 base_freq_hz;
> +	const struct brcmstb_match_priv *match_priv;
> +};
> +
> +static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
> +	void __iomem *cr = priv->cfg_regs;
> +	bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
> +
> +	if (is_emmc && priv->boot_regs)
> +		sr->boot_main_ctl = readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL);
> +
> +	if (ver == SDIO_CFG_CORE_V1) {
> +		sr->sd_pin_sel = readl(cr + SDIO_CFG_V1_SD_PIN_SEL);
> +		return;
> +	}
> +
> +	sr->sd_pin_sel = readl(cr + SDIO_CFG_SD_PIN_SEL);
> +	sr->phy_sw_mode0_rxctrl = readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
> +	sr->max_50mhz_mode = readl(cr + SDIO_CFG_MAX_50MHZ_MODE);
> +}
> +
> +static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
> +	void __iomem *cr = priv->cfg_regs;
> +	bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
> +
> +	if (is_emmc && priv->boot_regs)
> +		writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL);
> +
> +	if (ver == SDIO_CFG_CORE_V1) {
> +		writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
> +		return;
> +	}
> +
> +	writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
> +	writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
> +	writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE);
> +}
> +
> +static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int save)
> +{
> +	if (save)
> +		sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1);
> +	else
> +		sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1);
> +}
> +
> +static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int save)
> +{
> +	if (save)
> +		sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2);
> +	else
> +		sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2);
> +}
> +
>  static inline void enable_clock_gating(struct sdhci_host *host)
>  {
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> @@ -306,22 +387,26 @@ static struct brcmstb_match_priv match_priv_74371 = {
>  
>  static struct brcmstb_match_priv match_priv_7445 = {
>  	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
> +	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
>  	.ops = &sdhci_brcmstb_ops,
>  };
>  
>  static struct brcmstb_match_priv match_priv_72116 = {
>  	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
> +	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
>  	.ops = &sdhci_brcmstb_ops_72116,
>  };
>  
>  static const struct brcmstb_match_priv match_priv_7216 = {
>  	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
> +	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
>  	.hs400es = sdhci_brcmstb_hs400es,
>  	.ops = &sdhci_brcmstb_ops_7216,
>  };
>  
>  static struct brcmstb_match_priv match_priv_74165b0 = {
>  	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
> +	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
>  	.hs400es = sdhci_brcmstb_hs400es,
>  	.ops = &sdhci_brcmstb_ops_74165b0,
>  };
> @@ -429,6 +514,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
>  
>  	pltfm_host = sdhci_priv(host);
>  	priv = sdhci_pltfm_priv(pltfm_host);
> +	priv->match_priv = match->data;
>  	if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
>  		priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
>  		match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
> @@ -446,6 +532,13 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
>  	if (res)
>  		goto err;
>  
> +	/* map non-standard BOOT registers if present */
> +	if (host->mmc->caps & MMC_CAP_NONREMOVABLE) {
> +		priv->boot_regs = devm_platform_get_and_ioremap_resource(pdev, 2, NULL);
> +		if (IS_ERR(priv->boot_regs))
> +			priv->boot_regs = NULL;
> +	}
> +
>  	/*
>  	 * Automatic clock gating does not work for SD cards that may
>  	 * voltage switch so only enable it for non-removable devices.
> @@ -536,8 +629,13 @@ static int sdhci_brcmstb_suspend(struct device *dev)
>  	struct sdhci_host *host = dev_get_drvdata(dev);
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>  	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	const struct brcmstb_match_priv *match_priv = priv->match_priv;
> +
>  	int ret;
>  
> +	if (match_priv->save_restore_regs)
> +		match_priv->save_restore_regs(host->mmc, 1);
> +
>  	clk_disable_unprepare(priv->base_clk);
>  	if (host->mmc->caps2 & MMC_CAP2_CQE) {
>  		ret = cqhci_suspend(host->mmc);
> @@ -553,6 +651,7 @@ static int sdhci_brcmstb_resume(struct device *dev)
>  	struct sdhci_host *host = dev_get_drvdata(dev);
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>  	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	const struct brcmstb_match_priv *match_priv = priv->match_priv;
>  	int ret;
>  
>  	ret = sdhci_pltfm_resume(dev);
> @@ -569,6 +668,9 @@ static int sdhci_brcmstb_resume(struct device *dev)
>  			ret = clk_set_rate(priv->base_clk, priv->base_freq_hz);
>  	}
>  
> +	if (match_priv->save_restore_regs)
> +		match_priv->save_restore_regs(host->mmc, 0);
> +
>  	if (host->mmc->caps2 & MMC_CAP2_CQE)
>  		ret = cqhci_resume(host->mmc);
>  

Re: [PATCH v2 5/5] mmc: sdhci-brcmstb: save and restore registers during PM

[Adrian Hunter]

On 07/10/2025 17:04, Kamal Dasu wrote:
> Added support to save and restore registers that are critical
> during PM.
> 
> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-brcmstb.c | 112 +++++++++++++++++++++++++++++--
>  1 file changed, 107 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
> index 42709ca8111d..7de395c86f2f 100644
> --- a/drivers/mmc/host/sdhci-brcmstb.c
> +++ b/drivers/mmc/host/sdhci-brcmstb.c
> @@ -38,28 +38,109 @@
>  #define SDIO_CFG_OP_DLY_DEFAULT			0x80000003
>  #define SDIO_CFG_CQ_CAPABILITY			0x4c
>  #define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
> +#define SDIO_CFG_SD_PIN_SEL			0x44
> +#define SDIO_CFG_V1_SD_PIN_SEL			0x54
> +#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL		0x7C
>  #define SDIO_CFG_MAX_50MHZ_MODE			0x1ac
>  #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE	BIT(31)
>  #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE		BIT(0)
>  
> +#define SDIO_BOOT_MAIN_CTL			0x0
> +
>  #define MMC_CAP_HSE_MASK	(MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V)
>  /* Select all SD UHS type I SDR speed above 50MB/s */
>  #define MMC_CAP_UHS_I_SDR_MASK	(MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)
>  
> -struct sdhci_brcmstb_priv {
> -	void __iomem *cfg_regs;
> -	unsigned int flags;
> -	struct clk *base_clk;
> -	u32 base_freq_hz;
> +enum cfg_core_ver {
> +	SDIO_CFG_CORE_V1 = 1,
> +	SDIO_CFG_CORE_V2,
> +};
> +
> +struct sdhci_brcmstb_saved_regs {
> +	u32 sd_pin_sel;
> +	u32 phy_sw_mode0_rxctrl;
> +	u32 max_50mhz_mode;
> +	u32 boot_main_ctl;
>  };
>  
>  struct brcmstb_match_priv {
>  	void (*cfginit)(struct sdhci_host *host);
>  	void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
> +	void (*save_restore_regs)(struct mmc_host *mmc, int save);
>  	struct sdhci_ops *ops;
>  	const unsigned int flags;
>  };
>  
> +struct sdhci_brcmstb_priv {
> +	void __iomem *cfg_regs;
> +	void __iomem *boot_regs;
> +	struct sdhci_brcmstb_saved_regs saved_regs;
> +	unsigned int flags;
> +	struct clk *base_clk;
> +	u32 base_freq_hz;
> +	const struct brcmstb_match_priv *match_priv;
> +};
> +
> +static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
> +	void __iomem *cr = priv->cfg_regs;
> +	bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
> +
> +	if (is_emmc && priv->boot_regs)
> +		sr->boot_main_ctl = readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL);
> +
> +	if (ver == SDIO_CFG_CORE_V1) {
> +		sr->sd_pin_sel = readl(cr + SDIO_CFG_V1_SD_PIN_SEL);
> +		return;
> +	}
> +
> +	sr->sd_pin_sel = readl(cr + SDIO_CFG_SD_PIN_SEL);
> +	sr->phy_sw_mode0_rxctrl = readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
> +	sr->max_50mhz_mode = readl(cr + SDIO_CFG_MAX_50MHZ_MODE);
> +}
> +
> +static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
> +{
> +	struct sdhci_host *host = mmc_priv(mmc);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
> +	void __iomem *cr = priv->cfg_regs;
> +	bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
> +
> +	if (is_emmc && priv->boot_regs)
> +		writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL);
> +
> +	if (ver == SDIO_CFG_CORE_V1) {
> +		writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
> +		return;
> +	}
> +
> +	writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
> +	writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
> +	writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE);
> +}
> +
> +static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int save)
> +{
> +	if (save)
> +		sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1);
> +	else
> +		sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1);
> +}
> +
> +static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int save)
> +{
> +	if (save)
> +		sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2);
> +	else
> +		sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2);
> +}
> +
>  static inline void enable_clock_gating(struct sdhci_host *host)
>  {
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> @@ -306,22 +387,26 @@ static struct brcmstb_match_priv match_priv_74371 = {
>  
>  static struct brcmstb_match_priv match_priv_7445 = {
>  	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
> +	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
>  	.ops = &sdhci_brcmstb_ops,
>  };
>  
>  static struct brcmstb_match_priv match_priv_72116 = {
>  	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
> +	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
>  	.ops = &sdhci_brcmstb_ops_72116,
>  };
>  
>  static const struct brcmstb_match_priv match_priv_7216 = {
>  	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
> +	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
>  	.hs400es = sdhci_brcmstb_hs400es,
>  	.ops = &sdhci_brcmstb_ops_7216,
>  };
>  
>  static struct brcmstb_match_priv match_priv_74165b0 = {
>  	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
> +	.save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
>  	.hs400es = sdhci_brcmstb_hs400es,
>  	.ops = &sdhci_brcmstb_ops_74165b0,
>  };
> @@ -429,6 +514,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
>  
>  	pltfm_host = sdhci_priv(host);
>  	priv = sdhci_pltfm_priv(pltfm_host);
> +	priv->match_priv = match->data;
>  	if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
>  		priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
>  		match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
> @@ -446,6 +532,13 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
>  	if (res)
>  		goto err;
>  
> +	/* map non-standard BOOT registers if present */
> +	if (host->mmc->caps & MMC_CAP_NONREMOVABLE) {
> +		priv->boot_regs = devm_platform_get_and_ioremap_resource(pdev, 2, NULL);
> +		if (IS_ERR(priv->boot_regs))
> +			priv->boot_regs = NULL;
> +	}
> +
>  	/*
>  	 * Automatic clock gating does not work for SD cards that may
>  	 * voltage switch so only enable it for non-removable devices.
> @@ -536,8 +629,13 @@ static int sdhci_brcmstb_suspend(struct device *dev)
>  	struct sdhci_host *host = dev_get_drvdata(dev);
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>  	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	const struct brcmstb_match_priv *match_priv = priv->match_priv;
> +
>  	int ret;
>  
> +	if (match_priv->save_restore_regs)
> +		match_priv->save_restore_regs(host->mmc, 1);
> +
>  	clk_disable_unprepare(priv->base_clk);
>  	if (host->mmc->caps2 & MMC_CAP2_CQE) {
>  		ret = cqhci_suspend(host->mmc);
> @@ -553,6 +651,7 @@ static int sdhci_brcmstb_resume(struct device *dev)
>  	struct sdhci_host *host = dev_get_drvdata(dev);
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>  	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +	const struct brcmstb_match_priv *match_priv = priv->match_priv;
>  	int ret;
>  
>  	ret = sdhci_pltfm_resume(dev);
> @@ -569,6 +668,9 @@ static int sdhci_brcmstb_resume(struct device *dev)
>  			ret = clk_set_rate(priv->base_clk, priv->base_freq_hz);
>  	}
>  
> +	if (match_priv->save_restore_regs)
> +		match_priv->save_restore_regs(host->mmc, 0);
> +
>  	if (host->mmc->caps2 & MMC_CAP2_CQE)
>  		ret = cqhci_resume(host->mmc);
>  

Re: [PATCH v2 0/5] sdhci-brcmstb SD host controller SoC specific enhancements

[Ulf Hansson]

On Tue, 7 Oct 2025 at 16:04, Kamal Dasu <kamal.dasu@broadcom.com> wrote:
>
> sdhci-brcmstb HS200 configuration for BCM72116 and PM register save restore
> changes applicable to various SoCs.
>
> v2 changes:
>  - Separate commit for SDIO_CFG register defines that moved
>  - Implemented cosmetic changes proposed for initial change for :
>      "mmc: sdhci-brcmstb: clear CFG_OP_DLY when using HS200"
>  - Moved BCM74371 support in a separate commit
>  - Implemented review comments and reorganized code for :
>      "mmc: sdhci-brcmstb: save and restore registers during PM"
>  - Added Reviewed-by and Acked-by tags wherever applicable
>
> Kamal Dasu (5):
>   dt-bindings: mmc: Add support for BCM72116 and BCM74371 SD host
>     controller
>   mmc: sdhci-brcmstb: move SDIO_CFG_CQ_CAPABILITY define
>   mmc: sdhci-brcmstb: clear CFG_OP_DLY when using HS200
>   mmc: sdhci-brcmstb: Add BCM74371 support
>   mmc: sdhci-brcmstb: save and restore registers during PM
>
>  .../bindings/mmc/brcm,sdhci-brcmstb.yaml      |   2 +
>  drivers/mmc/host/sdhci-brcmstb.c              | 154 +++++++++++++++++-
>  2 files changed, 147 insertions(+), 9 deletions(-)
>

The series applied for next, thanks!

Kind regards
Uffe