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[81.167.86.93]) by smtp.gmail.com with ESMTPSA id v7-20020ac258e7000000b00486c14f0fe1sm1836729lfo.11.2022.07.23.14.02.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 23 Jul 2022 14:02:00 -0700 (PDT) Message-ID: <3b38996f-e887-9130-36d0-6a02efe2034e@linaro.org> Date: Sat, 23 Jul 2022 23:01:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 09/22] dt-bindings: clock: rockchip: Document RV1126 CRU Content-Language: en-US To: Jagan Teki , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Kever Yang Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Michael Turquette , Stephen Boyd References: <20220723204335.750095-1-jagan@edgeble.ai> <20220723204335.750095-10-jagan@edgeble.ai> From: Krzysztof Kozlowski In-Reply-To: <20220723204335.750095-10-jagan@edgeble.ai> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 23/07/2022 22:43, Jagan Teki wrote: > Document dt-bindings for Rockchip RV1126 clock controller. > > Cc: linux-clk@vger.kernel.org > Cc: Michael Turquette > Cc: Stephen Boyd > Signed-off-by: Jagan Teki > --- > .../bindings/clock/rockchip,rv1126-cru.yaml | 70 +++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml > new file mode 100644 > index 000000000000..cf4f11709125 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ROCKCHIP RV1126 Family Clock Control Module Binding s/Binding// > + > +maintainers: > + - Jagan Teki > + - Finley Xiao > + - Heiko Stuebner > + > +description: | You can skip '|'. No formatting in text. > + The RV1126 clock controller generates the clock and also implements a > + reset controller for SoC peripherals. > + > +properties: > + compatible: > + enum: > + - rockchip,rv1126-cru > + - rockchip,rv1126-pmucru > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + "#reset-cells": > + const: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: xin24m > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to the syscon managing the "general register files" (GRF), > + if missing pll rates are not changeable, due to the missing pll > + lock status. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - "#reset-cells" > + > +additionalProperties: false > + > +examples: > + - | > + pmucru: clock-controller@ff480000 { > + compatible = "rockchip,rv1126-pmucru"; > + reg = <0xff480000 0x1000>; > + rockchip,grf = <&grf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + - | > + cru: clock-controller@ff490000 { > + compatible = "rockchip,rv1126-cru"; > + reg = <0xff490000 0x1000>; > + rockchip,grf = <&grf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; I would keep just one example - they are the same, except compatible. Less code to manage or to fix later... With all the changes: Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof