* [PATCH v3] ARM: dts: stm32: Add ADC support to stm32mp157c
@ 2018-05-22 15:45 Fabrice Gasnier
2018-06-26 9:51 ` Alexandre Torgue
0 siblings, 1 reply; 2+ messages in thread
From: Fabrice Gasnier @ 2018-05-22 15:45 UTC (permalink / raw)
To: alexandre.torgue
Cc: robh+dt, mcoquelin.stm32, mark.rutland, linux-arm-kernel,
devicetree, linux-kernel, fabrice.gasnier
stm32mp157c has an ADC block with two physical ADCs.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
---
Changes in v3:
- Add dmas since dmamux1 has been added on top of stm32-next
---
arch/arm/boot/dts/stm32mp157c.dtsi | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index b66f673..66d7496 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -600,6 +600,42 @@
clocks = <&rcc DMAMUX>;
};
+ adc: adc@48003000 {
+ compatible = "st,stm32mp1-adc-core";
+ reg = <0x48003000 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+ clock-names = "bus", "adc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc1: adc@0 {
+ compatible = "st,stm32mp1-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ interrupt-parent = <&adc>;
+ interrupts = <0>;
+ dmas = <&dmamux1 9 0x400 0x01>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ adc2: adc@100 {
+ compatible = "st,stm32mp1-adc";
+ #io-channel-cells = <1>;
+ reg = <0x100>;
+ interrupt-parent = <&adc>;
+ interrupts = <1>;
+ dmas = <&dmamux1 10 0x400 0x01>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+ };
+
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
--
1.9.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH v3] ARM: dts: stm32: Add ADC support to stm32mp157c
2018-05-22 15:45 [PATCH v3] ARM: dts: stm32: Add ADC support to stm32mp157c Fabrice Gasnier
@ 2018-06-26 9:51 ` Alexandre Torgue
0 siblings, 0 replies; 2+ messages in thread
From: Alexandre Torgue @ 2018-06-26 9:51 UTC (permalink / raw)
To: Fabrice Gasnier
Cc: robh+dt, mcoquelin.stm32, mark.rutland, linux-arm-kernel,
devicetree, linux-kernel
Hi Fabrice
On 05/22/2018 05:45 PM, Fabrice Gasnier wrote:
> stm32mp157c has an ADC block with two physical ADCs.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> ---
> Changes in v3:
> - Add dmas since dmamux1 has been added on top of stm32-next
> ---
> arch/arm/boot/dts/stm32mp157c.dtsi | 36 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
> index b66f673..66d7496 100644
> --- a/arch/arm/boot/dts/stm32mp157c.dtsi
> +++ b/arch/arm/boot/dts/stm32mp157c.dtsi
Applied on stm32-next.
Thanks.
Alex
> @@ -600,6 +600,42 @@
> clocks = <&rcc DMAMUX>;
> };
>
> + adc: adc@48003000 {
> + compatible = "st,stm32mp1-adc-core";
> + reg = <0x48003000 0x400>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&rcc ADC12>, <&rcc ADC12_K>;
> + clock-names = "bus", "adc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + adc1: adc@0 {
> + compatible = "st,stm32mp1-adc";
> + #io-channel-cells = <1>;
> + reg = <0x0>;
> + interrupt-parent = <&adc>;
> + interrupts = <0>;
> + dmas = <&dmamux1 9 0x400 0x01>;
> + dma-names = "rx";
> + status = "disabled";
> + };
> +
> + adc2: adc@100 {
> + compatible = "st,stm32mp1-adc";
> + #io-channel-cells = <1>;
> + reg = <0x100>;
> + interrupt-parent = <&adc>;
> + interrupts = <1>;
> + dmas = <&dmamux1 10 0x400 0x01>;
> + dma-names = "rx";
> + status = "disabled";
> + };
> + };
> +
> rcc: rcc@50000000 {
> compatible = "st,stm32mp1-rcc", "syscon";
> reg = <0x50000000 0x1000>;
>
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2018-05-22 15:45 [PATCH v3] ARM: dts: stm32: Add ADC support to stm32mp157c Fabrice Gasnier
2018-06-26 9:51 ` Alexandre Torgue
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