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[2003:f6:ef10:f100:a045:a7a7:11d0:8676]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aabbe35c629sm259486866b.175.2024.12.17.03.57.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 03:57:53 -0800 (PST) Message-ID: <3bb6c6347b09ac62178f79ab53d52aebe867197f.camel@gmail.com> Subject: Re: [PATCH v6 11/17] iio: adc: ad7944: add support for SPI offload From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno =?ISO-8859-1?Q?S=E1?= Cc: Uwe =?ISO-8859-1?Q?Kleine-K=F6nig?= , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, Jonathan Cameron Date: Tue, 17 Dec 2024 13:02:24 +0100 In-Reply-To: <20241211-dlech-mainline-spi-engine-offload-2-v6-11-88ee574d5d03@baylibre.com> References: <20241211-dlech-mainline-spi-engine-offload-2-v6-0-88ee574d5d03@baylibre.com> <20241211-dlech-mainline-spi-engine-offload-2-v6-11-88ee574d5d03@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2024-12-11 at 14:54 -0600, David Lechner wrote: > Add support for SPI offload to the ad7944 driver. This allows reading > data at the max sample rate of 2.5 MSPS. >=20 > Reviewed-by: Jonathan Cameron > Signed-off-by: David Lechner > --- Reviewed-by: Nuno Sa >=20 > v6 changes: > * More detailed comments on offload channels info struct. (I didn't > =C2=A0 put them inside the macro because the multiline comments don't pla= y > =C2=A0 well with the line continuation "\".) >=20 > v5 changes: > * Remove dev_info() message. > * Implement sampling_frequency_available attribute. > * Limit max sample rate to chip-specific value. >=20 > v4 changes: > * Adapted to changes in other patches. > * Add new separate channel spec for when using SPI offload. > * Fixed some nitpicks. >=20 > v3 changes: > * Finished TODOs. > * Adapted to changes in other patches. >=20 > v2 changes: >=20 > In the previous version, there was a new separate driver for the PWM > trigger and DMA hardware buffer. This was deemed too complex so they > are moved into the ad7944 driver. >=20 > It has also been reworked to accommodate for the changes described in > the other patches. > --- > =C2=A0drivers/iio/adc/Kconfig=C2=A0 |=C2=A0=C2=A0 1 + > =C2=A0drivers/iio/adc/ad7944.c | 291 ++++++++++++++++++++++++++++++++++++= ++++++++-- > - > =C2=A02 files changed, 276 insertions(+), 16 deletions(-) >=20 > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig > index > a3e8ac569ce4c6b6b30b48acb265d530aa98e89c..995b9cacbaa964d26424346120c1398= 58f93 > cdcd 100644 > --- a/drivers/iio/adc/Kconfig > +++ b/drivers/iio/adc/Kconfig > @@ -360,6 +360,7 @@ config AD7923 > =C2=A0config AD7944 > =C2=A0 tristate "Analog Devices AD7944 and similar ADCs driver" > =C2=A0 depends on SPI > + select SPI_OFFLOAD > =C2=A0 select IIO_BUFFER > =C2=A0 select IIO_TRIGGERED_BUFFER > =C2=A0 help > diff --git a/drivers/iio/adc/ad7944.c b/drivers/iio/adc/ad7944.c > index > 6d1202bd55a013b092ff803f2065fd128dfa9bdd..07984eb450e82fc06d67fa0a157e3ae= 4e755 > 5678 100644 > --- a/drivers/iio/adc/ad7944.c > +++ b/drivers/iio/adc/ad7944.c > @@ -16,11 +16,14 @@ > =C2=A0#include > =C2=A0#include > =C2=A0#include > +#include > =C2=A0#include > =C2=A0#include > +#include > =C2=A0 > =C2=A0#include > =C2=A0#include > +#include > =C2=A0#include > =C2=A0#include > =C2=A0 > @@ -54,6 +57,12 @@ struct ad7944_adc { > =C2=A0 enum ad7944_spi_mode spi_mode; > =C2=A0 struct spi_transfer xfers[3]; > =C2=A0 struct spi_message msg; > + struct spi_transfer offload_xfers[2]; > + struct spi_message offload_msg; > + struct spi_offload *offload; > + struct spi_offload_trigger *offload_trigger; > + unsigned long offload_trigger_hz; > + int sample_freq_range[3]; > =C2=A0 void *chain_mode_buf; > =C2=A0 /* Chip-specific timing specifications. */ > =C2=A0 const struct ad7944_timing_spec *timing_spec; > @@ -81,6 +90,8 @@ struct ad7944_adc { > =C2=A0 > =C2=A0/* quite time before CNV rising edge */ > =C2=A0#define AD7944_T_QUIET_NS 20 > +/* minimum CNV high time to trigger conversion */ > +#define AD7944_T_CNVH_NS 10 > =C2=A0 > =C2=A0static const struct ad7944_timing_spec ad7944_timing_spec =3D { > =C2=A0 .conv_ns =3D 420, > @@ -95,7 +106,9 @@ static const struct ad7944_timing_spec ad7986_timing_s= pec =3D > { > =C2=A0struct ad7944_chip_info { > =C2=A0 const char *name; > =C2=A0 const struct ad7944_timing_spec *timing_spec; > + u32 max_sample_rate_hz; > =C2=A0 const struct iio_chan_spec channels[2]; > + const struct iio_chan_spec offload_channels[1]; > =C2=A0}; > =C2=A0 > =C2=A0/* get number of bytes for SPI xfer */ > @@ -105,13 +118,15 @@ struct ad7944_chip_info { > =C2=A0 * AD7944_DEFINE_CHIP_INFO - Define a chip info structure for a spe= cific chip > =C2=A0 * @_name: The name of the chip > =C2=A0 * @_ts: The timing specification for the chip > + * @_max: The maximum sample rate in Hz > =C2=A0 * @_bits: The number of bits in the conversion result > =C2=A0 * @_diff: Whether the chip is true differential or not > =C2=A0 */ > -#define AD7944_DEFINE_CHIP_INFO(_name, _ts, _bits, _diff) \ > +#define AD7944_DEFINE_CHIP_INFO(_name, _ts, _max, _bits, > _diff) \ > =C2=A0static const struct ad7944_chip_info _name##_chip_info =3D { \ > =C2=A0 .name =3D > #_name, \ > =C2=A0 .timing_spec =3D &_ts##_timing_spec, \ > + .max_sample_rate_hz =3D _max, \ > =C2=A0 .channels =3D { \ > =C2=A0 { \ > =C2=A0 .type =3D IIO_VOLTAGE, \ > @@ -129,13 +144,43 @@ static const struct ad7944_chip_info _name##_chip_i= nfo =3D > { \ > =C2=A0 }, \ > =C2=A0 IIO_CHAN_SOFT_TIMESTAMP(1), \ > =C2=A0 }, \ > + .offload_channels =3D { \ > + { \ > + .type =3D IIO_VOLTAGE, \ > + .indexed =3D 1, \ > + .differential =3D _diff, \ > + .channel =3D 0, \ > + .channel2 =3D _diff ? 1 : 0, \ > + .scan_index =3D 0, \ > + .scan_type.sign =3D _diff ? 's' : 'u', \ > + .scan_type.realbits =3D _bits, \ > + .scan_type.storagebits =3D 32, \ > + .scan_type.endianness =3D IIO_CPU, \ > + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) \ > + | BIT(IIO_CHAN_INFO_SCALE) \ > + | > BIT(IIO_CHAN_INFO_SAMP_FREQ), \ > + .info_mask_separate_available > =3D \ > + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ > + }, \ > + }, \ > =C2=A0} > =C2=A0 > +/* > + * Notes on the offload channels: > + * - There is no soft timestamp since everything is done in hardware. > + * - There is a sampling frequency attribute added. This controls the SP= I > + *=C2=A0=C2=A0 offload trigger. > + * - The storagebits value depends on the SPI offload provider. Currentl= y > there > + *=C2=A0=C2=A0 is only one supported provider, namely the ADI PULSAR ADC= HDL project, > + *=C2=A0=C2=A0 which always uses 32-bit words for data values, even for = <=3D 16-bit ADCs. > + *=C2=A0=C2=A0 So the value is just hardcoded to 32 for now. > + */ > + > =C2=A0/* pseudo-differential with ground sense */ > -AD7944_DEFINE_CHIP_INFO(ad7944, ad7944, 14, 0); > -AD7944_DEFINE_CHIP_INFO(ad7985, ad7944, 16, 0); > +AD7944_DEFINE_CHIP_INFO(ad7944, ad7944, 2.5 * MEGA, 14, 0); > +AD7944_DEFINE_CHIP_INFO(ad7985, ad7944, 2.5 * MEGA, 16, 0); > =C2=A0/* fully differential */ > -AD7944_DEFINE_CHIP_INFO(ad7986, ad7986, 18, 1); > +AD7944_DEFINE_CHIP_INFO(ad7986, ad7986, 2 * MEGA, 18, 1); > =C2=A0 > =C2=A0static int ad7944_3wire_cs_mode_init_msg(struct device *dev, struct > ad7944_adc *adc, > =C2=A0 const struct iio_chan_spec *chan) > @@ -239,6 +284,48 @@ static int ad7944_chain_mode_init_msg(struct device = *dev, > struct ad7944_adc *adc > =C2=A0 return devm_spi_optimize_message(dev, adc->spi, &adc->msg); > =C2=A0} > =C2=A0 > +/* > + * Unlike ad7944_3wire_cs_mode_init_msg(), this creates a message that r= eads > + * during the conversion phase instead of the acquisition phase when rea= ding > + * a sample from the ADC. This is needed to be able to read at the maxim= um > + * sample rate. It requires the SPI controller to have offload support a= nd a > + * high enough SCLK rate to read the sample during the conversion phase. > + */ > +static int ad7944_3wire_cs_mode_init_offload_msg(struct device *dev, > + struct ad7944_adc *adc, > + const struct iio_chan_spec > *chan) > +{ > + struct spi_transfer *xfers =3D adc->offload_xfers; > + int ret; > + > + /* > + * CS is tied to CNV and we need a low to high transition to start > the > + * conversion, so place CNV low for t_QUIET to prepare for this. > + */ > + xfers[0].delay.value =3D AD7944_T_QUIET_NS; > + xfers[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; > + /* CNV has to be high for a minimum time to trigger conversion. */ > + xfers[0].cs_change =3D 1; > + xfers[0].cs_change_delay.value =3D AD7944_T_CNVH_NS; > + xfers[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; > + > + /* Then we can read the previous sample during the conversion phase > */ > + xfers[1].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; > + xfers[1].len =3D AD7944_SPI_BYTES(chan->scan_type); > + xfers[1].bits_per_word =3D chan->scan_type.realbits; > + > + spi_message_init_with_transfers(&adc->offload_msg, xfers, > + ARRAY_SIZE(adc->offload_xfers)); > + > + adc->offload_msg.offload =3D adc->offload; > + > + ret =3D devm_spi_optimize_message(dev, adc->spi, &adc->offload_msg); > + if (ret) > + return dev_err_probe(dev, ret, "failed to prepare offload > msg\n"); > + > + return 0; > +} > + > =C2=A0/** > =C2=A0 * ad7944_convert_and_acquire - Perform a single conversion and acq= uisition > =C2=A0 * @adc: The ADC device structure > @@ -294,6 +381,23 @@ static int ad7944_single_conversion(struct ad7944_ad= c > *adc, > =C2=A0 return IIO_VAL_INT; > =C2=A0} > =C2=A0 > +static int ad7944_read_avail(struct iio_dev *indio_dev, > + =C2=A0=C2=A0=C2=A0=C2=A0 struct iio_chan_spec const *chan, > + =C2=A0=C2=A0=C2=A0=C2=A0 const int **vals, int *type, int *length, > + =C2=A0=C2=A0=C2=A0=C2=A0 long mask) > +{ > + struct ad7944_adc *adc =3D iio_priv(indio_dev); > + > + switch (mask) { > + case IIO_CHAN_INFO_SAMP_FREQ: > + *vals =3D adc->sample_freq_range; > + *type =3D IIO_VAL_INT; > + return IIO_AVAIL_RANGE; > + default: > + return -EINVAL; > + } > +} > + > =C2=A0static int ad7944_read_raw(struct iio_dev *indio_dev, > =C2=A0 =C2=A0=C2=A0 const struct iio_chan_spec *chan, > =C2=A0 =C2=A0=C2=A0 int *val, int *val2, long info) > @@ -326,13 +430,104 @@ static int ad7944_read_raw(struct iio_dev *indio_d= ev, > =C2=A0 return -EINVAL; > =C2=A0 } > =C2=A0 > + case IIO_CHAN_INFO_SAMP_FREQ: > + *val =3D adc->offload_trigger_hz; > + return IIO_VAL_INT; > + > + default: > + return -EINVAL; > + } > +} > + > +static int ad7944_set_sample_freq(struct ad7944_adc *adc, int val) > +{ > + struct spi_offload_trigger_config config =3D { > + .type =3D SPI_OFFLOAD_TRIGGER_PERIODIC, > + .periodic =3D { > + .frequency_hz =3D val, > + }, > + }; > + int ret; > + > + ret =3D spi_offload_trigger_validate(adc->offload_trigger, &config); > + if (ret) > + return ret; > + > + adc->offload_trigger_hz =3D config.periodic.frequency_hz; > + > + return 0; > +} > + > +static int ad7944_write_raw(struct iio_dev *indio_dev, > + =C2=A0=C2=A0=C2=A0 const struct iio_chan_spec *chan, > + =C2=A0=C2=A0=C2=A0 int val, int val2, long info) > +{ > + struct ad7944_adc *adc =3D iio_priv(indio_dev); > + > + switch (info) { > + case IIO_CHAN_INFO_SAMP_FREQ: > + if (val < 1 || val > adc->sample_freq_range[2]) > + return -EINVAL; > + > + return ad7944_set_sample_freq(adc, val); > =C2=A0 default: > =C2=A0 return -EINVAL; > =C2=A0 } > =C2=A0} > =C2=A0 > +static int ad7944_write_raw_get_fmt(struct iio_dev *indio_dev, > + =C2=A0=C2=A0=C2=A0 const struct iio_chan_spec *chan, > + =C2=A0=C2=A0=C2=A0 long mask) > +{ > + switch (mask) { > + case IIO_CHAN_INFO_SAMP_FREQ: > + return IIO_VAL_INT; > + default: > + return IIO_VAL_INT_PLUS_MICRO; > + } > +} > + > =C2=A0static const struct iio_info ad7944_iio_info =3D { > + .read_avail =3D &ad7944_read_avail, > =C2=A0 .read_raw =3D &ad7944_read_raw, > + .write_raw =3D &ad7944_write_raw, > + .write_raw_get_fmt =3D &ad7944_write_raw_get_fmt, > +}; > + > +static int ad7944_offload_buffer_postenable(struct iio_dev *indio_dev) > +{ > + struct ad7944_adc *adc =3D iio_priv(indio_dev); > + struct spi_offload_trigger_config config =3D { > + .type =3D SPI_OFFLOAD_TRIGGER_PERIODIC, > + .periodic =3D { > + .frequency_hz =3D adc->offload_trigger_hz, > + }, > + }; > + int ret; > + > + gpiod_set_value_cansleep(adc->turbo, 1); > + > + ret =3D spi_offload_trigger_enable(adc->offload, adc->offload_trigger, > + &config); > + if (ret) > + gpiod_set_value_cansleep(adc->turbo, 0); > + > + return ret; > +} > + > +static int ad7944_offload_buffer_predisable(struct iio_dev *indio_dev) > +{ > + struct ad7944_adc *adc =3D iio_priv(indio_dev); > + > + spi_offload_trigger_disable(adc->offload, adc->offload_trigger); > + gpiod_set_value_cansleep(adc->turbo, 0); > + > + return 0; > +} > + > +static const struct iio_buffer_setup_ops ad7944_offload_buffer_setup_ops= =3D { > + .postenable =3D &ad7944_offload_buffer_postenable, > + .predisable =3D &ad7944_offload_buffer_predisable, > =C2=A0}; > =C2=A0 > =C2=A0static irqreturn_t ad7944_trigger_handler(int irq, void *p) > @@ -446,6 +641,11 @@ static const char * const ad7944_power_supplies[] = =3D { > =C2=A0 "avdd", "dvdd", "bvdd", "vio" > =C2=A0}; > =C2=A0 > +static const struct spi_offload_config ad7944_offload_config =3D { > + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | > + =C2=A0=C2=A0=C2=A0 SPI_OFFLOAD_CAP_RX_STREAM_DMA, > +}; > + > =C2=A0static int ad7944_probe(struct spi_device *spi) > =C2=A0{ > =C2=A0 const struct ad7944_chip_info *chip_info; > @@ -471,6 +671,10 @@ static int ad7944_probe(struct spi_device *spi) > =C2=A0 > =C2=A0 adc->timing_spec =3D chip_info->timing_spec; > =C2=A0 > + adc->sample_freq_range[0] =3D 1; /* min */ > + adc->sample_freq_range[1] =3D 1; /* step */ > + adc->sample_freq_range[2] =3D chip_info->max_sample_rate_hz; /* max */ > + > =C2=A0 ret =3D device_property_match_property_string(dev, "adi,spi-mode", > =C2=A0 =C2=A0=C2=A0=C2=A0 ad7944_spi_modes, > =C2=A0 =C2=A0=C2=A0=C2=A0 > ARRAY_SIZE(ad7944_spi_modes)); > @@ -590,20 +794,74 @@ static int ad7944_probe(struct spi_device *spi) > =C2=A0 indio_dev->modes =3D INDIO_DIRECT_MODE; > =C2=A0 indio_dev->info =3D &ad7944_iio_info; > =C2=A0 > - if (adc->spi_mode =3D=3D AD7944_SPI_MODE_CHAIN) { > - indio_dev->available_scan_masks =3D chain_scan_masks; > - indio_dev->channels =3D chain_chan; > - indio_dev->num_channels =3D n_chain_dev + 1; > + adc->offload =3D devm_spi_offload_get(dev, spi, > &ad7944_offload_config); > + ret =3D PTR_ERR_OR_ZERO(adc->offload); > + if (ret && ret !=3D -ENODEV) > + return dev_err_probe(dev, ret, "failed to get offload\n"); > + > + /* Fall back to low speed usage when no SPI offload available. */ > + if (ret =3D=3D -ENODEV) { > + if (adc->spi_mode =3D=3D AD7944_SPI_MODE_CHAIN) { > + indio_dev->available_scan_masks =3D chain_scan_masks; > + indio_dev->channels =3D chain_chan; > + indio_dev->num_channels =3D n_chain_dev + 1; > + } else { > + indio_dev->channels =3D chip_info->channels; > + indio_dev->num_channels =3D ARRAY_SIZE(chip_info- > >channels); > + } > + > + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > iio_pollfunc_store_time, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ad7944_trigger_handler, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 NULL); > + if (ret) > + return ret; > =C2=A0 } else { > - indio_dev->channels =3D chip_info->channels; > - indio_dev->num_channels =3D ARRAY_SIZE(chip_info->channels); > - } > + struct dma_chan *rx_dma; > =C2=A0 > - ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 iio_pollfunc_store_time, > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ad7944_trigger_handler, NULL); > - if (ret) > - return ret; > + if (adc->spi_mode !=3D AD7944_SPI_MODE_SINGLE) > + return dev_err_probe(dev, -EINVAL, > + "offload only supported in single mode\n"); > + > + indio_dev->setup_ops =3D &ad7944_offload_buffer_setup_ops; > + indio_dev->channels =3D chip_info->offload_channels; > + indio_dev->num_channels =3D ARRAY_SIZE(chip_info- > >offload_channels); > + > + adc->offload_trigger =3D devm_spi_offload_trigger_get(dev, > + adc->offload, SPI_OFFLOAD_TRIGGER_PERIODIC); > + if (IS_ERR(adc->offload_trigger)) > + return dev_err_probe(dev, PTR_ERR(adc- > >offload_trigger), > + =C2=A0=C2=A0=C2=A0=C2=A0 "failed to get offload > trigger\n"); > + > + ret =3D ad7944_set_sample_freq(adc, 2 * MEGA); > + if (ret) > + return dev_err_probe(dev, ret, > + =C2=A0=C2=A0=C2=A0=C2=A0 "failed to init sample rate\n"); > + > + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, > + =C2=A0=C2=A0=C2=A0=C2=A0 adc- > >offload); > + if (IS_ERR(rx_dma)) > + return dev_err_probe(dev, PTR_ERR(rx_dma), > + =C2=A0=C2=A0=C2=A0=C2=A0 "failed to get offload RX > DMA\n"); > + > + /* > + * REVISIT: ideally, we would confirm that the offload RX DMA > + * buffer layout is the same as what is hard-coded in > + * offload_channels. Right now, the only supported offload > + * is the pulsar_adc project which always uses 32-bit word > + * size for data values, regardless of the SPI bits per word. > + */ > + > + ret =3D devm_iio_dmaengine_buffer_setup_with_handle(dev, > + indio_dev, rx_dma, IIO_BUFFER_DIRECTION_IN); > + if (ret) > + return ret; > + > + ret =3D ad7944_3wire_cs_mode_init_offload_msg(dev, adc, > + &chip_info->offload_channels[0]); > + if (ret) > + return ret; > + } > =C2=A0 > =C2=A0 return devm_iio_device_register(dev, indio_dev); > =C2=A0} > @@ -638,3 +896,4 @@ module_spi_driver(ad7944_driver); > =C2=A0MODULE_AUTHOR("David Lechner "); > =C2=A0MODULE_DESCRIPTION("Analog Devices AD7944 PulSAR ADC family driver"= ); > =C2=A0MODULE_LICENSE("GPL"); > +MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); >=20