From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 123D3C433F5 for ; Wed, 11 May 2022 14:50:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245111AbiEKOuh (ORCPT ); Wed, 11 May 2022 10:50:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245099AbiEKOue (ORCPT ); Wed, 11 May 2022 10:50:34 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E23E1B0922 for ; Wed, 11 May 2022 07:50:26 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id a30so2911578ljq.9 for ; Wed, 11 May 2022 07:50:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=ElWpfj0wGJL50TvRphg5kRjDcZaYvuq2GbVsqJVFYCc=; b=D89wtlNLbOs5yE8adcQ/A2ga2mHXKALISGT/gYSnpbat0i4NuirW4ZCbyUo2MTqHIM DybTUguFzP50B+QC5CPz2TzKjbooVf6vopYcNNMl7ZUovlVPA0oH8Br/q9KFIEAmXniz F0j2NDH2h9QX+6DPv05OnLKU/lCRS2VNa6DQznqwmQB3VBxMPm5cCJbbSmyddqzOtzgw MErApNu6AJbzoTmjvacV0Cjlufn2JPHd7IFrZPxtZuKzx5w77hCDKAFQUpVM50td0iZT WgQtdLpvHIwe6pWOO3tlZhkYS3rM9lzdvgLUrwrDhiGGSwVnAz5iQAYClQs/zR9hV3u3 p17Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=ElWpfj0wGJL50TvRphg5kRjDcZaYvuq2GbVsqJVFYCc=; b=nloDfBzd0uNvjNPhlc//lv1eub6Dnrtve6LGQV+/ytX8frdQ+SXyJOqu0u0rudCyVu FPe16mCO8/LntYAJeHOqbI9nvrxZOzV0us1fHfMetb2EwPlWNniNdeI8MndR0E6tY/8P U9YeL/PJyQqi6YbOBVSjWwgI/o3CQL++agK2+ChDpknn9dFbVDOcLifsDDOGHxUaPWxh txrCQBkg4BVQrbLOCEJ+SsQNG2bqdFTpLJeK8tgCpTzRe53pdUUsjL6XrD3el3seYg1z UfYpZUDlYVLei971mEhwFFXhKIx2ZJpYU8R1kJzN300ixkoXcrnhS6PoCteX6jpWJ9Kb SSgA== X-Gm-Message-State: AOAM530gHVI2cSiOM/KIJhbOfBqVjG6ruI4kQ6wiK934S5jN1syKM2kS /YEohJs8CU+p0PjXZkZi1TJi3Q== X-Google-Smtp-Source: ABdhPJywfHPoACVHlBO9DahbBv/k/o1jSWDDDk9EmMhQ1LcoWNLUQAhoA0UwVt6duF/93+DZe8i4Pw== X-Received: by 2002:a2e:9e02:0:b0:249:7d50:bd8c with SMTP id e2-20020a2e9e02000000b002497d50bd8cmr17118916ljk.327.1652280624969; Wed, 11 May 2022 07:50:24 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id d17-20020ac25ed1000000b0047255d2116bsm315476lfq.154.2022.05.11.07.50.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 May 2022 07:50:24 -0700 (PDT) Message-ID: <3c126a06-f8fb-bc7a-860b-d4b1f2ef0133@linaro.org> Date: Wed, 11 May 2022 17:50:23 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: [PATCH v7 6/7] dt-bindings: PCI: qcom: Support additional MSI interrupts Content-Language: en-GB To: Rob Herring Cc: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski References: <20220505135407.1352382-1-dmitry.baryshkov@linaro.org> <20220505135407.1352382-7-dmitry.baryshkov@linaro.org> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 06/05/2022 00:30, Rob Herring wrote: > On Thu, May 05, 2022 at 04:54:06PM +0300, Dmitry Baryshkov wrote: >> On Qualcomm platforms each group of 32 MSI vectors is routed to the >> separate GIC interrupt. Document mapping of additional interrupts. >> >> Reviewed-by: Krzysztof Kozlowski >> Signed-off-by: Dmitry Baryshkov >> --- >> .../devicetree/bindings/pci/qcom,pcie.yaml | 45 ++++++++++++++++++- >> 1 file changed, 44 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> index 0b69b12b849e..fd3290e0e220 100644 >> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> @@ -43,11 +43,20 @@ properties: >> maxItems: 5 >> >> interrupts: >> - maxItems: 1 >> + minItems: 1 >> + maxItems: 8 >> >> interrupt-names: >> + minItems: 1 >> items: >> - const: msi >> + - const: msi2 > > Is 2 from some documentation or you made up. If the latter, software > folks start numbering at 0, not 1. :) I wouldn't care, but I think this > may become common. It has been made up, so I will update this. > >> + - const: msi3 >> + - const: msi4 >> + - const: msi5 >> + - const: msi6 >> + - const: msi7 >> + - const: msi8 -- With best wishes Dmitry