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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v2 0/9] PCI: rockchip: Fix RK3399 PCIe endpoint controller driver Content-Language: en-US To: Rick Wertenbroek Cc: alberto.dassatti@heig-vd.ch, xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Jani Nikula , Rodrigo Vivi , Mikko Kovanen , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> From: Damien Le Moal Organization: Western Digital Research In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 3/14/23 16:57, Rick Wertenbroek wrote: > On Tue, Mar 14, 2023 at 1:02=E2=80=AFAM Damien Le Moal > wrote: >> >> On 2/14/23 23:08, Rick Wertenbroek wrote: >>> This is a series of patches that fixes the PCIe endpoint controller d= river >>> for the Rockchip RK3399 SoC. The driver was introduced in >>> cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe control= ler") >>> The original driver had issues and would not allow for the RK3399 to >>> operate in PCIe endpoint mode correctly. This patch series fixes that= so >>> that the PCIe core controller of the RK3399 SoC can now act as a PCIe >>> endpoint. This is v2 of the patch series and addresses the concerns t= hat >>> were raised during the review of the first version. >> >> Rick, >> >> Are you going to send a rebased V3 soon ? I have a couple of additiona= l >> patches to add on top of your series... >> >=20 > I'll try to send a V3 this week. The changes to V2 will be the issues > raised and discussed on the V2 here in the mailing list with the additi= onal > code for removing the unsupported MSI-X capability list (was discussed > in the mailing list as well). Thanks. Additional patch needed to avoid problems with this controller is that we need to set ".align =3D 256" in the features. Otherwise, things do not work well. This is because the ATU drops the low 8-bits of the PCI addresses. It is a one liner patch, so feel free to add it to your series= . I also noticed random issues wich seem to be due to link-up timing... We probably will need to implement a poll thread to detect and notify with the linkup callback when we actually have the link established with the host (see the dw-ep controller which does something similar). From: Damien Le Moal Date: Thu, 9 Mar 2023 16:37:24 +0900 Subject: [PATCH] PCI: rockchip: Set address alignment for endpoint mode The address translation unit of the rockchip EP controller does not use the lower 8 bits of a PCIe-space address to map local memory. Thus we must set the align feature field to 256 to let the user know about this constraint. Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 12db9a9d92af..c6a23db84967 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -471,6 +471,7 @@ static const struct pci_epc_features rockchip_pcie_epc_features =3D { .linkup_notifier =3D false, .msi_capable =3D true, .msix_capable =3D false, + .align =3D 256, }; static const struct pci_epc_features* --=20 2.39.2 --=20 Damien Le Moal Western Digital Research